关键词: DRAM结构设计, 行缓存, 功耗消耗, 多线程, VRB机制

Abstract: Currently, the processors improve system performance by increasing the number of cores and simultaneously running threads. However, increasing the number of processor cores and threads which share the memory system will decrease the memory row-buffer hit rate (RBHR), causing more memory power consumption and longer memory access latencies. We design and develop a fine-grained victim row-buffer (VRB) memory system to solve this problem. VRB mechanism provides an additional row-buffer (VRB) which temporarily stores the expelled data due to the row-buffer (RB) conflict for a possible access in the near future. This mechanism mitigates the multi-threaded interference phenomenon and increases the reuse ratio of row-buffer data in DRAM and avoids unnecessary accesses of the array of cells, thus some row activations, precharge operations and data transmission activities can be reduced. VRB can improve system performance and power consumption while incurring minor hardware complexity. Through full-system cycle-accurate simulations of many threads applications, we demonstrate that VRB mechanism achieves an up to 17.6% (8.7% on average) system-level throughput improvement, an up to 142.9% (51.4% on average) RBHR improvement, and saves an up to 17.6% (9.2% on average) power consumption compared with an 8-core Intel Xeon server.

Key words: DRAM architecture design, row buffer (RB), power consumption, multi-threaded, victim row-buffer (VRB) mechanism