ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2015, Vol. 52 ›› Issue (11): 2577-2588.doi: 10.7544/issn1000-1239.2015.20148178

• 系统结构 • 上一篇    下一篇

一种缓解多线程访存干扰的VRB内存机制

高珂1,3,范东睿1,刘志勇1,2   

  1. 1(计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京 100190); 2(北京市移动计算和新型终端重点实验室(中国科学院计算技术研究所) 北京 100190); 3(中国科学院大学 北京 100049) (gaoke@ict.ac.cn)
  • 出版日期: 2015-11-01
  • 基金资助: 
    基金项目:国家“九七三”重点基础研究发展计划基金项目(2011CB302501);国家自然科学基金项目(61020106002,61221062);NSFC与香港RGC合作项目(61161160566);“核高基”国家科技重大专项基金项目(2013ZX0102-8001-001-001)

Decoupling Contention with VRB Mechanism for Multi-Threaded Applications

Gao Ke1,3, Fan Dongrui1, Liu Zhiyong1,2   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190);2(Beijing Key Laboratory of Mobile Computing and New Terminals (Institute of Computing Technology, Chinese Academy of Sciences ), Beijing 100190);3(University of Chinese Academy of Sciences, Beijing 100049)
  • Online: 2015-11-01

摘要: 目前处理器通过持续增加核数和同时执行的线程数来提高系统性能.但是,增加共享内存的处理器核数和线程数会使得存储器中的行缓存(row-buffer, RB)命中率下降,造成存储器访问功耗增加和访存延迟增加.设计并开发了一种细粒度的victim row-buffer(VRB)内存机制系统来解决此问题.VRB机制提供附加的行缓存(VRB),暂时缓存由于行缓存(RB)冲突而从行缓存(RB)逐出的数据,以备后续可能的访问.这种机制缓解了多线程冲突,增加了DRAM中行缓存数据的重用率,避免了不必要的内存数据阵列的访问、行激活和预充电、数据传输等电路动作,可以通过少量的硬件代价提高内存系统的性能,并节约系统的功耗消耗.通过时序精确的全系统模拟器实验,对比8核的Intel Xeon处理器,所提出的VRB机制可以达到最高17.6%(平均8.7%)的系统级吞吐率改善、最高142.9%(平均51.4%)的行缓存命中率改善以及最高17.6%(平均9.2%)的系统功耗改善.

关键词: DRAM结构设计, 行缓存, 功耗消耗, 多线程, VRB机制

Abstract: Currently, the processors improve system performance by increasing the number of cores and simultaneously running threads. However, increasing the number of processor cores and threads which share the memory system will decrease the memory row-buffer hit rate (RBHR), causing more memory power consumption and longer memory access latencies. We design and develop a fine-grained victim row-buffer (VRB) memory system to solve this problem. VRB mechanism provides an additional row-buffer (VRB) which temporarily stores the expelled data due to the row-buffer (RB) conflict for a possible access in the near future. This mechanism mitigates the multi-threaded interference phenomenon and increases the reuse ratio of row-buffer data in DRAM and avoids unnecessary accesses of the array of cells, thus some row activations, precharge operations and data transmission activities can be reduced. VRB can improve system performance and power consumption while incurring minor hardware complexity. Through full-system cycle-accurate simulations of many threads applications, we demonstrate that VRB mechanism achieves an up to 17.6% (8.7% on average) system-level throughput improvement, an up to 142.9% (51.4% on average) RBHR improvement, and saves an up to 17.6% (9.2% on average) power consumption compared with an 8-core Intel Xeon server.

Key words: DRAM architecture design, row buffer (RB), power consumption, multi-threaded, victim row-buffer (VRB) mechanism

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