ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2015, Vol. 52 ›› Issue (6): 1316-1328.doi: 10.7544/issn1000-1239.2015.20150119

所属专题: 2015面向应用领域需求的体系结构

• 系统结构 • 上一篇    下一篇

面向高性能计算的众核处理器轻量级错误恢复技术研究

郑方,沈莉,李宏亮,谢向辉   

  1. (数学工程与先进计算国家重点实验室 江苏无锡 214125) (zheng.fang@meac-skl.cn)
  • 出版日期: 2015-06-01
  • 基金资助: 
    基金项目:国家“八六三”高技术研究发展计划基金项目(2014AA01A301);“核高基”国家科技重大专项基金项目(2013ZX0102-8001-001-001)

Lightweight Error Recovery Techniques of Many-Core Processor in High Performance Computing

Zheng Fang, Shen Li, Li Hongliang, Xie Xianghui   

  1. (State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi, Jiangsu 214125)
  • Online: 2015-06-01

摘要: 随着半导体技术进步,单个芯片上集成大量核心的众核处理器已经广泛应用于高性能计算领域.相比多核处理器,众核处理器能提供更好的计算密度和能效比,但同时也面临越来越严重的可靠性挑战.需要设计高效的处理器容错机制,有效保证课题运行效率的同时不带来较大的芯片功耗和面积开销.在一款自主众核处理器DFMC(deeply fused and heterogeneous many-core)原型基础上,根据核心上运行的应用程序是否具有关联性特征,提出并实现了面向众核处理器的独立和协同2种轻量级错误恢复技术.其中,协同恢复技术由集中部件进行管理,通过协同恢复总线互连,出错时将与错误相关联的多个核心快速回卷到正确状态.2种错误恢复技术中,保留和恢复过程均通过定制的指令实现,恢复所需要的信息保留在运算核心内部,以保证对课题性能的影响最小化.实验表明,通过上述技术只增加了1.257%的芯片面积,可解决自主众核处理器约80%的瞬时错误,且对课题性能、芯片时序和功耗影响很小,可有效地提高众核处理器的容错能力.

关键词: 众核处理器, 错误恢复, 容错, 瞬态错误, 高性能计算

Abstract: Due to the advances in semiconductor techniques, many-core processors with a large number of cores have been widely used in high-performance computing. Compared with multi-core processors, many-core processors can provide higher computing density and ratio of computation to power consumption. However, many-core processors must design more efficient fault tolerance mechanism to solve the serious reliability problem and alleviate performance degradation, while the cost of chip area and power must be low. In this paper, we present a prototype of home-grown many-core processor DFMC(deeply fused and heterogeneous many-core). Referring to the processor’s architecture and the applications related to the characters among cores, independent and coordinated lightweight error recovery techniques are proposed. When errors are detected, the related cores can roll back to consistent recovery line quickly by coordinated error recovery technique which is controlled by centralized unit and connected by coordinated recovery bus. To guarantee the applications’ performance, error recovery techniques are performed by instructions and recovery states are saved in cores. Our experimental results show that the effect of the techniques is significant, and the transient errors can be corrected by 80% with the chip area increased by 1.257%. The influences of lightweight error recovery techniques on applications performance, chip frequency and chip power consumption are very little. The techniques can improve the fault tolerant ability of the many-core processor.

Key words: many-core processor, error recovery, fault-tolerant, transient errors, high performance computing

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