ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2017, Vol. 54 ›› Issue (12): 2833-2842.doi: 10.7544/issn1000-1239.2017.20160670

• 信息安全 • 上一篇    下一篇

基于流体系架构的分组密码处理器设计

李功丽1,2,戴紫彬1,徐进辉1,王寿成1,朱玉飞1,冯晓1   

  1. 1(解放军信息工程大学 郑州 450001); 2(河南师范大学计算机与信息工程学院 河南新乡 453002) (ligl522@163.com)
  • 出版日期: 2017-12-01
  • 基金资助: 
    国家自然科学基金项目(61404175)

Design of Block Cipher Processor Based on Stream Architecture

Li Gongli1,2, Dai Zibin1, Xu Jinhui1, Wang Shoucheng1, Zhu Yufei1, Feng Xiao1   

  1. 1(PLA Information Engineering University, Zhengzhou 450001); 2(College of Computer & Information Engineering, Henan Normal University, Xinxiang, Henan 453002)
  • Online: 2017-12-01

摘要: 为提升密码处理器性能,构建了密码处理器性能模型.基于该模型,提出多级资源共享、绑定前/后异或操作、最大化算法并行度等处理器性能提升技术,并根据性能提升技术确定了功能单元的种类和数量.然而功能单元不仅数量较多,而且在操作位宽和操作延迟方面均有较大差异,如何有效组织这些功能单元成为了一个关键问题.利用流体系结构可以高效集成大量功能单元的特点,设计并实现了基于流体系结构的可重构分组密码处理器原型,并通过把功能单元划分为基本处理单元,bank间共享单元和簇间共享单元3个层次来解决功能单元处理位宽和操作延迟的差异.在65nm CMOS工艺下对处理器原型进行综合,并在该结构上映射了典型的分组密码算法.实验结果证明:该处理器以较小的面积获得了较高的性能,对典型分组密码算法的处理速度,不仅超越了国际上的密码专用指令处理器,而且高于国内可重构阵列结构密码处理器.

关键词: 分组密码, 流处理器, 性能模型, 可重构, 密码处理器

Abstract: To improve the performance of cipher processor, the performance model of cipher processor is proposed. And based on this model, three ways for enhancing cipher processor's performance are presented, which are sharing multi-level resources, binding operations of pre-xor or post-xor and maximizing parallelism of block cipher algorithms. According to these improvement methods, the type and amount of cryptographic function units are determined. However, the function units are not only numerous but also different in operation data width and latency, so how to organize these function units efficiently becomes a key problem. The stream processor architecture can integrate a large number of function units to obtain high performance. Then, we design and implement a reconfigurable block cipher processor prototype which is based on stream processor architecture, and in order to organize the numerous function units effectively, the function units are divided into basic units, inter-bank-shared units and inter-cluster-shared units respectively according to their processing width. The prototype is synthesized in 65nm CMOS process and several typical block cipher algorithms are mapped on it. The evaluation results show that the processor prototype is area-efficient and its performance is not only beyond that of international application specific instruction cipher processors, but also higher than that of the domestic reconfigurable array processors.

Key words: block cipher, stream processor, performance model, reconfigurable, cipher processor

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