ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2019, Vol. 56 ›› Issue (1): 35-48.doi: 10.7544/issn1000-1239.2019.20180771

• 系统结构 • 上一篇    下一篇

芯片敏捷开发实践:标签化RISC-V

余子濠1,2,刘志刚1,2,李一苇1,2,黄博文1,王卅1,2,孙凝晖1,2,包云岗1,2   

  1. 1(计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京 100190); 2(中国科学院大学 北京 100049) (yuzihao@ict.ac.cn)
  • 出版日期: 2019-01-01
  • 基金资助: 
    国家重点研发计划项目(2016YFB1000201);国家自然科学基金项目(61420106013, 61702480);中国科学院青年创新促进会(2013073)

Practice of Chip Agile Development: Labeled RISC-V

Yu Zihao1,2, Liu Zhigang1,2, Li Yiwei1,2, Huang Bowen1, Wang Sa1,2, Sun Ninghui1,2, Bao Yungang1,2   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190); 2(University of Chinese Academy of Sciences, Beijing 100049)
  • Online: 2019-01-01

摘要: 随着开放指令集RISC-V的流行,开源芯片的概念逐渐进入人们的视野.但是目前的芯片设计项目需要投入相当的人力和时间才能开展,并且具有一定的风险,这些情况一定程度上限制了开源芯片的发展.为了进一步降低芯片开发的门槛,加州大学伯克利分校先后设计了开放指令集RISC-V,开放了其SoC实现Rocket Chip的项目源码,并提出了一门面向敏捷开发的硬件构建语言Chisel.RISC-V,Rocket Chip和Chisel是如何赋能开源芯片敏捷开发?将基于中国科学院计算技术研究所的研究工作“标签化RISC-V”项目开发过程中的若干案例,展示:1)开放又活跃的指令集生态(如RISC-V)是推动芯片研发创新的必要条件;2)Chisel的信号整体连接、元编程、面向对象编程以及函数式编程等特性可大幅缩减代码量,提升代码可维护性;3)敏捷开发能在编码效率提升一个数量级的同时,达到与传统硬件开发模式相当甚至更优的性能、功耗与面积.

关键词: RISC-V, Chisel, 开源, 芯片设计, 敏捷开发

Abstract: Current chip design projects require considerable manpower and time to carry out, and have certain risks. These conditions have limited the development of open-sourced chip design to some extent. To further reduce the threshold for chip development, research teams at University of California, Berkeley have designed the open ISA RISC-V. They also open-sourced the Rocket Chip project, the SoC implementation of RISC-V, and put forward Chisel, a new hardware construction language, for agile development. How do RISC-V, Rocket Chip and Chisel enable open-source chip agile development? With some case studies during the development of the Labeled RISC-V project led by the Institute of Computing Technology, Chinese Academy of Sciences, this article shows: 1) An open and active ISA ecosystem (such as RISC-V) is a necessary condition to promote chip innovation; 2) Chisel’s features such as bulk connection, metaprogramming, object-oriented programming, and functional programming, can greatly reduce the amount of code and improve code maintainability; 3) Agile development can achieve an order of magnitude improvement in coding efficiency, while achieving comparable or even better performance, power consumption and area overhead than traditional hardware development models.

Key words: RISC-V, Chisel, open-source, chip design, agile development

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