ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2019, Vol. 56 ›› Issue (6): 1149-1160.doi: 10.7544/issn1000-1239.2019.20190099

所属专题: 2019面向人工智能的计算机体系结构专题

• 系统结构 • 上一篇    下一篇

基于3D忆阻器阵列的神经网络内存计算架构

毛海宇,舒继武   

  1. (清华大学计算机科学与技术系 北京 100084) (mhy15@mails.tsinghua.edu.cn)
  • 出版日期: 2019-06-01
  • 基金资助: 
    国家重点研发计划项目(2018YFB1003301);国家自然科学基金项目(61832011)

3D Memristor Array Based Neural Network Processing in Memory Architecture

Mao Haiyu, Shu Jiwu   

  1. (Department of Computer Science and Technology, Tsinghua University, Beijing 100084)
  • Online: 2019-06-01
  • Supported by: 
    This work was supported by the National Key Research and Development Program of China (2018YFB1003301) and the National Natural Science Foundation of China (61832011).

摘要: 现如今,由于人工智能的飞速发展,基于忆阻器的神经网络内存计算(processing in memory, PIM)架构吸引了很多研究者的兴趣,因为其性能远优于传统的冯·诺依曼计算机体系结构的性能.配备了支持功能单元的外围电路,忆阻器阵列可以以高并行度以及相比于CPU和GPU更少的数据移动来处理一个前向传播.然而,基于忆阻器的内存计算硬件存在忆阻器的外围电路面积过大以及不容忽视的功能单元利用率过低的问题.提出了一种基于3D忆阻器阵列的神经网络内存计算架构FMC(function-pool based memristor cube),通过把实现功能单元的外围电路聚集到一起,形成一个功能单元池来供多个堆叠在其上的忆阻器阵列共享.还提出了一种针对基于3D忆阻器阵列的内存计算的数据映射策略,进一步提高功能单元的利用率并减少忆阻器立方体之间的数据传输.这种针对基于3D忆阻器阵列的内存计算的软硬件协同设计不仅充分利用了功能单元,并且缩短了互联电路、提供了高性能且低能耗的数据传输.实验结果表明:在只训练单个神经网络时,提出的FMC能使功能单元的利用率提升43.33倍;在多个神经网络训练任务的情况下,能提升高达58.51倍.同时,和有相同数目的Compute Array及Storage Array的2D-PIM比较,FMC所占空间仅为2D-PIM的42.89%.此外,FMC相比于2D-PIM有平均1.5倍的性能提升,并且有平均1.7倍的能耗节约.

关键词: 3D忆阻器阵列, 内存计算, 神经网络, 外围电路, 互联线路

Abstract: Nowadays, due to the rapid development of artificial intelligence, the memristor-based processing in memory (PIM) architecture for neural network (NN) attracts a lot of researchers’ interests since it performs much better than traditional von Neumann architecture. Equipped with the peripheral circuit to support function units, memristor arrays can process a forward propagation with higher parallelism and much less data movement than that in CPU and GPU. However, the hardware of the memristor-based PIM suffers from the large area overhead of peripheral circuit outside the memristor array and non-trivial under-utilization of function units. This paper proposes a 3D memristor array based PIM architecture for NNs (FMC) by gathering the peripheral circuit of function units into a function pool for sharing among memristor arrays that pile up on the pool. We also propose a data mapping scheme for the 3D memristor array based PIM architecture to further increase the utilization of function units and reduce the data transmission among different cubes. The software-hardware co-design for the 3D memristor array based PIM not only makes the most of function units but also shortens the wire interconnections for better high-performance and energy-efficient data transmission. Experiments show that when training a single neural network, our proposed FMC can achieve up to 43.33 times utilization of the function units and can achieve up to 58.51 times utilization of the function units when training multiple neural networks. At the same time, compared with the 2D-PIM which has the same amount of compute array and storage array, FMC only occupies 42.89% area of 2D-PIM. What’s more, FMC has 1.5 times speedup and 1.7 times energy saving compared with 2D-PIM.

Key words: 3D memristor array, processing in memory (PIM), neural network, peripheral circuit, wire interconnection

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