ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2019, Vol. 56 ›› Issue (6): 1192-1204.doi: 10.7544/issn1000-1239.2019.20190117

所属专题: 2019面向人工智能的计算机体系结构专题

• 系统结构 • 上一篇    下一篇

基于细粒度数据流架构的稀疏神经网络全连接层加速

向陶然1,2,叶笑春1,李文明1,冯煜晶1,2,谭旭1,2,张浩1,范东睿1,2   

  1. 1(计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京 100190);2(中国科学院大学 北京 100049) (xiangtaoran@ict.ac.cn)
  • 出版日期: 2019-06-01
  • 基金资助: 
    国家重点研发计划项目(2018YFB1003501);国家自然科学基金项目(61732018,61872335,61802367);中国科学院国际伙伴计划(171111KYSB20170032);计算机体系结构国家重点实验室创新项目(CARCH3303,CARCH3407,CARCH3502,CARCH3505)

Accelerating Fully Connected Layers of Sparse Neural Networks with Fine-Grained Dataflow Architectures

Xiang Taoran1,2, Ye Xiaochun1, Li Wenming1, Feng Yujing1,2, Tan Xu1,2 , Zhang Hao1, Fan Dongrui1,2   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190);2(University of Chinese Academy of Sciences, Beijing 100049)
  • Online: 2019-06-01
  • Supported by: 
    This work was supported by the National Key Research and Development Plan of China (2018YFB1003501), the National Natural Science Foundation of China (61732018, 61872335, 61802367), the International Partnership Program of Chinese Academy of Sciences (171111KYSB20170032), and the Innovation Project of the State Key Laboratory of Computer Architecture (CARCH3303, CARCH3407, CARCH3502, CARCH3505).

摘要: 深度神经网络(deep neural network, DNN)是目前最先进的图像识别算法,被广泛应用于人脸识别、图像识别、文字识别等领域.DNN具有极高的计算复杂性,为解决这个问题,近年来涌出了大量可以并行运算神经网络的硬件加速器.但是,DNN中的全连接层有大量的权重参数,对加速器的带宽提出了很高的要求.为了减轻加速器的带宽压力,一些DNN压缩算法被提出.然而基于FPGA和ASIC的DNN专用加速器,通常是通过牺牲硬件的灵活性获得更高的加速比和更低的能耗,很难实现稀疏神经网络的加速.而另一类基于CPU,GPU的CNN加速方案虽然较为灵活,但是带来很高的能耗.细粒度数据流体系结构打破了传统的控制流结构的限制,展示出了加速DNN的天然优势,它在提供高性能的运算能力的同时也保持了一定的灵活性.为此,提出了一种在基于细粒度数据流体系结构的硬件加速器上加速稀疏的DNN全连接层的方案.该方案相较于原有稠密的全连接层的计算减少了2.44×~ 6.17×的峰值带宽需求.此外细粒度数据流加速器在运行稀疏全连接层时的计算部件利用率远超过其他硬件平台对稀疏全连接层的实现,平均比CPU,GPU和mGPU分别高了43.15%,34.57%和44.24%.

关键词: 细粒度数据流, 稀疏神经网络, 通用加速器, 数据重用, 高并行性

Abstract: Deep neural network (DNN) is a hot and state-of-the-art algorithm which is widely used in applications such as face recognition, intelligent monitoring, image recognition and text recognition. Because of its high computational complexity, many efficient hardware accelerators have been proposed to exploit high degree of parallel processing for DNN. However, the fully connected layers in DNN have a large number of weight parameters, which imposes high requirements on the bandwidth of the accelerator. In order to reduce the bandwidth pressure of the accelerator, some DNN compression algorithms are proposed. But accelerators which are implemented on FPGAs and ASICs usually sacrifice generality for higher performance and lower power consumption, making it difficult to accelerate sparse neural networks. Other accelerators, such as GPUs, are general enough, but they lead to higher power consumption. Fine-grained dataflow architectures, which break conventional Von Neumann architectures, show natural advantages in processing DNN-like algorithms with high computational efficiency and low power consumption. At the same time, it remains broadly applicable and adaptable. In this paper, we propose a scheme to accelerate the sparse DNN fully connected layers on a hardware accelerator based on fine-grained dataflow architecture. Compared with the original dense fully connected layers, the scheme reduces the peak bandwidth requirement of 2.44×~ 6.17×. In addition, the utilization of the computational resource of the fine-grained dataflow accelerator running the sparse fully-connected layers far exceeds the implementation by other hardware platforms, which is 43.15%, 34.57%, and 44.24% higher than the CPU, GPU, and mGPU, respectively.

Key words: fine-grained dataflow, sparse neural network, general accelerator, data reuse, high parallel

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