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    何卫锋 毛志刚 吕志强 尹海丰. 一种基于FBMA算法的整像素运动估计芯片的VLSI设计[J]. 计算机研究与发展, 2005, 42(7): 1225-1230.
    引用本文: 何卫锋 毛志刚 吕志强 尹海丰. 一种基于FBMA算法的整像素运动估计芯片的VLSI设计[J]. 计算机研究与发展, 2005, 42(7): 1225-1230.
    He Weifeng, Mao Zhigang, Lü Zhiqiang, and Yin Haifeng. VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor[J]. Journal of Computer Research and Development, 2005, 42(7): 1225-1230.
    Citation: He Weifeng, Mao Zhigang, Lü Zhiqiang, and Yin Haifeng. VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor[J]. Journal of Computer Research and Development, 2005, 42(7): 1225-1230.

    一种基于FBMA算法的整像素运动估计芯片的VLSI设计

    VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor

    • 摘要: 给出了一种基于全搜索块匹配算法的运动估计电路的改进结构,并完成了VLSI设计.通过采用多端口匹配策略和双时钟方案,使得在提高先前帧搜索区域像素数据重复利用率的同时,将脉动阵列的计算效率提高到74.9%. 采用TSMC 0.25μm 1P5M CMOS工艺, 完成了运动估计芯片的VLSI实现,其芯片面积为3.37mm×3.37mm, 最高工作频率为110MHz. 综合后仿真表明在89.4MHz的频率下,该电路可以对支持MPEG-4 AS Profile标准的ITU-R601格式视频图像(720×480@30Hz/NTSC或720×576@25Hz/PAL)进行基于整像素的实时运动估计.

       

      Abstract: An improved architecture for motion estimation using the full-search block-matching algorithm is proposed in this paper. To reduce the utilization of the global bus to the external memory and to improve the data reuse efficiency of search frame pixels, a multi-port matching scheme and double clock strategy are adopted. Compared with the previous FBMA architecture, this new architecture achieves 74.9% processor utilization as well as improves the reuse efficiency of search area pixel data. The motion estimation processor is implemented using the TSMC 0.25μm 1-poly 5-metal CMOS technology, which occupies a silicon area of 3.37mm×3.37mm and operates at 110MHz. Experimental results show that it is able to estimate full pixel motion vectors of MPEG-4 AS profile sequences in ITU-R601 format (720×480@30Hz/NTSC or 720×576@25Hz/PAL) in real-time at around 89.4MHz

       

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