用于WCET静态分析的MIPS处理器建模方法研究

Study on Modeling MIPS Processors for Static WCET Analysis

摘要: 为获得安全而紧致的WCET估计，需要考虑执行程序的目标处理器的体系结构特征. Cache、流水线等用于提高性能的技术已经广泛地应用于现代处理器中，如果在静态分析过程中不考虑它们带来的影响，必然会导致WCET过估计.以Petri网作为模型工具，以WCET分析为应用目标构造MIPS处理器的体系结构模型，该方法讨论了各种RISC处理器中常见的体系结构特征的抽象以及它们在Petri网模型中的表示方法.通过实验验证，指令序列在Petri网模型上的模拟执行时间与指令序列在DLXView模拟器上的测试结果具有一致性，表明构建处理器的体系结构Petri网模型是一种有效的指令序列执行时间的静态分析方法.

Abstract: To obtain safe and tight WCET estimation, it is necessary to take account of the features of a target processor architecture. New architecture mechanisms, such as cache, pipeline etc., have been widely applied in modern processors to increas their performance. Ignoring their impact will cause WCET overestimated during the analysis of execution time. For the purpose of WCET analysis, a method of modeling MIPS processor architecture is proposed using Petri nets. How to abstract common RISC processor architecture features and how to model them with Petri nets are discussed and its effectivity is verified with experiment.