Abstract: In this paper, a VLSI design and ASIC implementation of a pretty low cost RSA cryptosystem is presented, which is based on the modified Montgomery algorithm and the Chinese remainder Theory (CRT), By adopting a novel scheduling method, we realize 1152-bit modular exponentiation with 576-bit modular multiplier unit, which reduces the hardware complexity greatly. And by using the CRT technique, a comparable throughput with general 1024-bit RSA cryptosystem is achieved. The experimental result shows that a 1024-bit modular exponentiation calculation can be performed in about 1.2 mega cycles, and less than 54K gates are needed. With 40MHz system clock, a signature rate of over 30Kbps can be achieved.