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    张 戈 齐子初 胡伟武. 龙芯2号处理器功能部件设计[J]. 计算机研究与发展, 2006, 43(6): 967-973.
    引用本文: 张 戈 齐子初 胡伟武. 龙芯2号处理器功能部件设计[J]. 计算机研究与发展, 2006, 43(6): 967-973.
    Zhang Ge, Qi Zichu, and Hu Weiwu. Functional Units Design in Godson-2 Processor[J]. Journal of Computer Research and Development, 2006, 43(6): 967-973.
    Citation: Zhang Ge, Qi Zichu, and Hu Weiwu. Functional Units Design in Godson-2 Processor[J]. Journal of Computer Research and Development, 2006, 43(6): 967-973.

    龙芯2号处理器功能部件设计

    Functional Units Design in Godson-2 Processor

    • 摘要: 功能部件是处理器中进行指令运算的核心单元,它的算法及其实现直接影响到处理器的总体性能.介绍了龙芯2号处理器的功能部件,探讨了从算法到物理设计等不同层次的功能部件设计方法.龙芯2号功能部件分为两个定点ALU和两个浮点ALU实现,除实现完整的MIPS定、浮点指令集外,还实现了龙芯2号类MMX自定义多媒体指令集以及定点操作在浮点部件(FPU)中的数据通路复用.龙芯2号浮点部件遵照IEEE754和MIPS相关标准,浮点加法4拍完成,浮点乘法5拍完成,浮点除法4~17拍完成.物理设计支持0.18μm工艺下主频500MHz的标准单元实现,浮点单精度峰值性能达到2GFLOPS,双精度峰值性能达到1GFLOPS.

       

      Abstract: The algorithm and its implementation of functional units are very vital for the performance of today's state of art general-purpose microprocessor design. An overview of the functional units design in Godson-2 processor is given and some details including architecture and physical design are described. Godson-2 has two fixed-point functional units: ALU1 and ALU2, and two floating-point units (FPU): FALU1 and FALU2. The MMX-like instructions are also implemented in Godson2 FPU. The FPU is IEEE-754 and MIPS compliant. The floating-point adder and multiplier have 4-cycle and 5-cycle latencies respectively, and the floating-point division has various 4~17 cycle latencies. The physical design based on the standard cell methodology with SMIC 0.18μm CMOS technology show that 2Gflops for single precision and 1Gflops for double precision performance are achieved with the speed of 500MHZ.

       

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