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    李志强, 陈汉武, 徐宝文, 刘文杰. 基于Hash表的量子可逆逻辑电路综合的快速算法[J]. 计算机研究与发展, 2008, 45(12): 2162-2171.
    引用本文: 李志强, 陈汉武, 徐宝文, 刘文杰. 基于Hash表的量子可逆逻辑电路综合的快速算法[J]. 计算机研究与发展, 2008, 45(12): 2162-2171.
    Li Zhiqiang, Chen Hanwu, Xu Baowen, Liu Wenjie. Fast Algorithms for Synthesis of Quantum Reversible Logic Circuits Based on Hash Table[J]. Journal of Computer Research and Development, 2008, 45(12): 2162-2171.
    Citation: Li Zhiqiang, Chen Hanwu, Xu Baowen, Liu Wenjie. Fast Algorithms for Synthesis of Quantum Reversible Logic Circuits Based on Hash Table[J]. Journal of Computer Research and Development, 2008, 45(12): 2162-2171.

    基于Hash表的量子可逆逻辑电路综合的快速算法

    Fast Algorithms for Synthesis of Quantum Reversible Logic Circuits Based on Hash Table

    • 摘要: 量子可逆逻辑电路是构建量子计算机的基本单元,通过量子门的级联与组合构成量子计算机,量子可逆逻辑电路的综合就是根据电路功能,以较小的量子代价自动构造量子可逆逻辑电路.结合可逆逻辑电路综合的多种算法,提出了一种新颖高效的量子电路综合算法,巧妙构造最小完备的Hash函数,可使用多种量子门,采用任意量子代价标准,以极高的效率生成最优的量子可逆逻辑电路.为实现量子电路综合的自动化,首次提出了利用量子线的置换自动构造各种量子门库的通用算法.采用国际同行认可的3变量可逆函数测试标准,该算法不仅能够生成全部最优电路,而且运行速度远远超过其他算法.实验结果表明,该算法按最小长度、最小代价标准综合电路的平均速度分别是目前最好结果的49.15倍、365.13倍.

       

      Abstract: Quantum reversible logic circuits are basic elements of quantum computer. The quantum computer can be constructed by cascading and combining the quantum gates. Synthesis of quantum reversible logic circuits automatically constructs the desired quantum reversible logic circuits with minimal quantum cost. By absorbing all kinds of ideas of synthesis of reversible logic circuits, a novel and efficient algorithm is presented, which can construct optimal quantum reversible logic circuits with various types of gates and quantum costs by constructing minimal perfect Hash function. A universal algorithm is proposed, which can automatically construct all kinds of quantum gate libraries through the permutations of quantum lines, to ensure the realization of the automation of quantum circuit synthesis. Judging by the internationally recognized reversible functions of three variables, the algorithm presented not only synthesizes all optimal reversible logic circuits, but also runs extremely faster than other ones. The experimental results show that the average speed of the algorithm, which synthesizes circuit with minimum length or at minimum cost, is 49.15 and 365.13 times that of currently best result respectively.

       

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