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    贾惠柱, 解晓东, 高 文. 基于软硬件分区的AVS高清视频解码器结构[J]. 计算机研究与发展, 2008, 45(3): 510-518.
    引用本文: 贾惠柱, 解晓东, 高 文. 基于软硬件分区的AVS高清视频解码器结构[J]. 计算机研究与发展, 2008, 45(3): 510-518.
    Jia Huizhu, Xie Xiaodong, Gao Wen. An AVS HDTV Video Decoder Architecture Based on HW/SW Partitioning[J]. Journal of Computer Research and Development, 2008, 45(3): 510-518.
    Citation: Jia Huizhu, Xie Xiaodong, Gao Wen. An AVS HDTV Video Decoder Architecture Based on HW/SW Partitioning[J]. Journal of Computer Research and Development, 2008, 45(3): 510-518.

    基于软硬件分区的AVS高清视频解码器结构

    An AVS HDTV Video Decoder Architecture Based on HW/SW Partitioning

    • 摘要: 硬件的强大处理能力及软件的灵活性和可编程性,使得视频解码芯片的结构从硬件转向软硬件分区结构.作为新兴的标准,AVS视频标准对解码器的软硬件分区结构提出新的挑战.从AVS视频标准算法和实现复杂度入手,提出一种AVS高清视频解码器软硬件分区结构,实现满足基准档次6.0级别的AVS高清视频码流的实时解码,支持灵活的音视频同步、错误恢复、缓冲区管理和系统控制机制.已经在AVS101芯片上实现,硬件采用7阶宏块级同步流水,软件任务在RISC处理器上实现,可以在148.5MHz工作频率下对NTSC,PAL,720p(60f/s),直至1080i(60field/s)节目的实时解码显示.

       

      Abstract: Video decoder architecture is developing from dedicated hardware to HW/SW partition, this owes to the powerful process of hardware and the flexibility and programmability of software. The increasing complexity of AVS algorithms has raised the challenge for HW/SW partitioning architecture. In this paper, AVS algorithms and complexity are first analyzed. Based on the analysis, an optimized real-time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder with HW/SW portioning is proposed. It can support real-time AVS JiZhun profile 6.0 level video decoding, and also support flexible A/V synchronization, error recovery, buffer management and system control mechanism. A hardware implementation of the MB level 7-stage synchronized pipeline is selected. The software tasks are realized with a 32-bit RISC processor. Under the control of the RSIC processor, the design can support AVS video syntax extension and revision in the future. The AVS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip AVS HDTV real-time decoder. At 148.5MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 f/s or 1080i@60 field/s) bit-streams. Finally, the decoder chip has been physically implemented in AVS101 on a 6-metal 0.18μm SMIC CMOS technology and fully tested on a prototyping board.

       

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