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    鲍 丹 向 波 申 睿 陈 赟 曾晓洋. 基于TDMP优化算法的QC-LDPC译码器VLSI实现[J]. 计算机研究与发展, 2009, 46(2): 338-344.
    引用本文: 鲍 丹 向 波 申 睿 陈 赟 曾晓洋. 基于TDMP优化算法的QC-LDPC译码器VLSI实现[J]. 计算机研究与发展, 2009, 46(2): 338-344.
    Bao Dan, Xiang Bo, Shen Rui, Chen Yun, and Zeng Xiaoyang. VLSI Implementation of QC-LDPC Decoder Using Optimized TDMP Algorithm[J]. Journal of Computer Research and Development, 2009, 46(2): 338-344.
    Citation: Bao Dan, Xiang Bo, Shen Rui, Chen Yun, and Zeng Xiaoyang. VLSI Implementation of QC-LDPC Decoder Using Optimized TDMP Algorithm[J]. Journal of Computer Research and Development, 2009, 46(2): 338-344.

    基于TDMP优化算法的QC-LDPC译码器VLSI实现

    VLSI Implementation of QC-LDPC Decoder Using Optimized TDMP Algorithm

    • 摘要: 在对TDMP算法优化的基础上,提出了一种LDPC译码器VLSI架构和实现方法.与目前已经存在的LDPC译码器相比,这种实现方法的优势主要有:1)能够实现快速收敛,将译码迭代次数降低为经典方法的50%以下,进而降低功耗;2)用于存储中间置信信息的存储器使用量比传统方法减少50%以上,大大减少芯片面积;3)校验节点置信度更新采用归一化Min-Sum算法(NMS),降低计算复杂度,选取的校正因子保证了译码器的BER性能;4)充分利用校验矩阵的准循环特点,实现规整的芯片内部互连线,减小布线难度.用这种架构实现了符合中国数字电视地面传输标准(DTMB)的LDPC译码器:融合3种码率;芯片规模为58万门;时钟频率为100MHz,数据吞吐率为107Mbps.

       

      Abstract: An area and power efficient VLSI architecture is presented for QC-LDPC decoder based on optimized turbo-decoding message-passing (TDMP) algorithm. The optimization is based mainly on the check node updating using normalized Min-Sum (NMS) scheme, which has been proposed for the two-phase message-passing (TPMP) algorithm or the so called two-phase belief propagation algorithm. The primary advantages of the proposed architecture over recent work are: 1) power dissipation reduction resulting from fast convergence speed by a factor of larger than 2 in terms of decoding iterations, 2) more than 50% savings in memory leading to a large chip area reduction benefiting from memory optimization by posterior message compression, 3) good performance and low complexity resulting in small area and low power due to normalized Min-Sum algorithm for check-node updating, and 4) reducing interconnection congestion by making full use of quasi-cyclic characteristics of check matrix and the proposed logarithm shifters. The proposed architecture is implemented in the Chinese Digital Television Terrestrial Multimedia Broadcasting (DTMB) system for LDPC codes decoding. The decoder consumes 0.58 million gates, and reaches a throughput of 107Mbps at a clock frequency of 100MHz. The proposed architecture can be extended to other digital communication systems such as wireless local area network (WLAN), etc, which adopt LDPC codes as the forward error correction (FEC) scheme.

       

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