Abstract: Computer architecture simulator is an important tool for computer architecture researchers. Recent development of parallel architectures bring great challenge to computer simulations. On the target side, as processors move towards multi-core and many-core, the complexity of the target system is doubling in the speed of Moore’s law as the simulated target core number grows; on the host side, the speed of sequential simulation is halted as the speed of a single host processor halts. Due to the above two reasons, sequential simulation could no longer meet the challenge of new parallel architectures. In this paper, we will describe the necessity and feasibility of parallel simulation for parallel computer architectures using two examples: a many-core processor simulator and a many-core cluster simulator. For many-core processor simulator, we use parallel discrete event simulation (PDES) to speed it up 10.9 times without accuracy lost. For many-core cluster simulation, we simulated a cluster at 1024-core scale, with MPI/Pthreads runtime support.