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    邵恩, 元国军, 郇志轩, 曹政, 孙凝晖. 面向大规模计算集群的多轨分割网络[J]. 计算机研究与发展, 2017, 54(11): 2534-2546. DOI: 10.7544/issn1000-1239.2017.20151069
    引用本文: 邵恩, 元国军, 郇志轩, 曹政, 孙凝晖. 面向大规模计算集群的多轨分割网络[J]. 计算机研究与发展, 2017, 54(11): 2534-2546. DOI: 10.7544/issn1000-1239.2017.20151069
    Shao En, Yuan Guojun, Huan Zhixuan, Cao Zheng, Sun Ninghui. A Sliced Multi-Rail Interconnection Network for Large-Scale Clusters[J]. Journal of Computer Research and Development, 2017, 54(11): 2534-2546. DOI: 10.7544/issn1000-1239.2017.20151069
    Citation: Shao En, Yuan Guojun, Huan Zhixuan, Cao Zheng, Sun Ninghui. A Sliced Multi-Rail Interconnection Network for Large-Scale Clusters[J]. Journal of Computer Research and Development, 2017, 54(11): 2534-2546. DOI: 10.7544/issn1000-1239.2017.20151069

    面向大规模计算集群的多轨分割网络

    A Sliced Multi-Rail Interconnection Network for Large-Scale Clusters

    • 摘要: 在千万亿次规模的系统中,互连网络设计面临新的挑战.高性能节点和大规模是构建千万亿次系统的主要技术趋势,不断提高的节点计算能力要求互连网络提供更高的性能,而不断增大的规模又对互连网络扩展性提出了更高的要求.此外,随着系统规模的增大,集合通信的执行时间也在不断增长,制约了应用的扩展性,集合通信的性能需要得到进一步优化.除性能之外,可靠性问题也随着系统规模的扩大而日益严重.而随着计算节点性能的不断提高,互连网络逐渐成为限制大规模计算机系统性能的瓶颈.互连网络核心部件交换芯片可提供的聚合网络带宽受到工艺和封装技术的限制.从网络结构与交换机结构的协同设计思想出发,提出了一种在交换机聚合带宽限定的条件下多轨分割网络结构和设计方法.通过数学建模和网络模拟仿真,分析了该多轨分割网络的性能边界.评测结果表明:该网络可将短消息(长度小于128B)的平均延迟性能提高10倍以上,为以短消息占多数的数据中心网络的性能优化提供了新思路.

       

      Abstract: In large-scale clusters, the design of interconnection network is facing greater challenges. Firstly, the increasing computing capacity of a single node requires the network providing higher bandwidth and lower latency. Secondly, the increasing number of nodes requires the network to have extremely better scalability. Thirdly, the increasing scale of system leads to worse performance of collective communication, which is harmful to the performance and scalability of applications. Fourthly, the increasing number of devices requires the network to have better reliability. As the performance of computing nodes keeps increasing, interconnection network has gradually become the bottleneck of large-scale computing system. However, switch chip, the core component of interconnection network, can offer limited aggregate bandwidth because of the constraint of physical processes and packaging technologies. With the co-design of network architecture and switch micro-architecture, this paper proposes a sliced multi-rail network architecture regarding the given aggregate bandwidth. Through mathematical modeling and network simulation, we studies the performance boundaries of sliced multi-rail network. Evaluation results show that the average latency of the short message (less than 128B)can be increased by more than 10 times.

       

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