The VLSI Design of AVS Entropy Coder

For the hardware accelerator of AVS high definition video encoder (AVS-HD), an efficient VLSI design for AVS entropy coder (2D-VLC) is provided. Firstly, due to the pipeline operation and parallel processing of hardware, the corresponding parallel algorithm from the original serial algorithm based on software architecture is proposed. Secondly, the VLSI design of entropy coder for mode decision is simplified with only logical operations, which can save much hardware memory. In the stage of mode decision, the bit-width of each DCT coefficient is only needed without the knowledge of its whole symbols, so the pure logical operations instead of looking up table required by the final entropy encoder are employed. Using the proposed hardware accelerator of AVS entropy coder, the computing complexity and memory requirement of hardware are both reduced. Moreover, in the VLSI design, the processing of hardware is further accelerated by employing 8-pixel parallel pipelining design. In such pipelining design, 8 DCT coefficients after quantization are processed in one time clock. For VLC of AVS, the CodeNumber of each (run, level) which is derived from zigzag, is obtained by looking up VLC tables. And then, each CodeNumber is mapped into code word written into the final bit stream. Such processing is same as those of other VLC coders, so the VLSI design can be used in other video coding standards, such as H.264/AVC and MPEG2/4. Finally, the result of software and RTL simulation indicate that the VLSI design is absolutely consistent with the AVS standard, and satisfied with the requirement of hardware accelerator.