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    龚小航, 蒋滨泽, 陈香兰, 高银康, 李曦. 实时计算机系统结构综述[J]. 计算机研究与发展, 2023, 60(5): 1021-1036. DOI: 10.7544/issn1000-1239.202220731
    引用本文: 龚小航, 蒋滨泽, 陈香兰, 高银康, 李曦. 实时计算机系统结构综述[J]. 计算机研究与发展, 2023, 60(5): 1021-1036. DOI: 10.7544/issn1000-1239.202220731
    Gong Xiaohang, Jiang Binze, Chen Xianglan, Gao Yinkang, Li Xi. Survey of Real-Time Computer System Architecture[J]. Journal of Computer Research and Development, 2023, 60(5): 1021-1036. DOI: 10.7544/issn1000-1239.202220731
    Citation: Gong Xiaohang, Jiang Binze, Chen Xianglan, Gao Yinkang, Li Xi. Survey of Real-Time Computer System Architecture[J]. Journal of Computer Research and Development, 2023, 60(5): 1021-1036. DOI: 10.7544/issn1000-1239.202220731

    实时计算机系统结构综述

    Survey of Real-Time Computer System Architecture

    • 摘要: 在时间敏感的嵌入式系统中,任务需要满足其最后截止期限,错失任务期限会显著影响服务质量或带来灾难性后果. 与通用系统相比,实时系统研究进展缓慢,甚至很多基本概念都未达成共识. 精确计时(precision timed,PRET)机和实时处理单元(real-time processing unit,RPU)是2套现有的实时系统解决方案,以它们为例介绍实时系统相关的概念,阐述实时系统发展中遇到的问题,比较异同,并分析实时系统各个层次遇到的问题和现有的解决方法. 在应用层,用户需要定时操作的接口;在指令集架构(instruction set architecture,ISA)层,应充分利用硬件提供的资源,向上层提供足够的时间语义抽象和计时精度;硬件层需要支持ISA的时间属性和时间语义,并在保证实时性的基础上尽可能地提高性能. 对实时系统的研究面临许多挑战. 在现有的实时系统设计研究的过程中,关键问题在于上层应用的时间语义难以与底层实现保持一致.

       

      Abstract: In time-sensitive embedded systems, tasks need to meet their deadlines, and missing deadlines can significantly affect the quality of service or have catastrophic consequences. Compared with the general system, the research progress of real-time system is slow, even many basic concepts have not reached consensus. Precision timed (PRET) machine and real-time processing unit (RPU) are two existing real-time system solutions. Taking them as examples, we introduce the related concepts of real-time system, expound the problems in the development of real-time system, and compare the similarities and differences. The problems encountered at each level of the real-time system and the existing solutions are analyzed. At the application layer, the user needs an interface for periodic operations; in instruction set architecture (ISA) layer, resources provided by hardware should be fully utilized to provide sufficient semantic abstraction and timing precision to the upper layer. The hardware layer needs to support ISA's time attributes and time semantics, and to improve performance as much as possible while ensuring real-time performance. Research on real-time systems faces many challenges. In the process of designing and researching the existing real-time system, the key problem is that the time semantics of the upper application is difficult to keep consistent with the lower implementation.

       

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