抗差分功耗分析攻击的AES算法的VLSI实现

VLSI Implementation of an AES Algorithm Resistant to Differential Power Analysis Attack

摘要: 提出了一种抗差分功耗分析攻击的先进密码算法(AES)的低成本的VLSI实现方案.采用屏蔽(masking)技术来抗差分功耗分析攻击.为了降低抗攻击技术对原有运算单元速度面积的影响，在分析改进的AES算法的基础上，用优化运算次序、复用相应模块、采用复合域计算等方法实现了以极小的硬件代价获得了较高的抗攻击性能.采用HHNEC 0.25μm标准CMOS工艺，单元面积约48×10\+3等效门；在70MHz工作频率下，数据吞吐率达到380Mbps.

Abstract: Proposed in this paper is a low cost VLSI implementation of an AES algorithm resistant to DPA (differential power analysis) attack using masking. In order to minimize the influence of the modification on the hardware while enabling it to be resistant to DPA, methods such as altering calculation order, module reuse and composite field computation to reduce chip area and maintain its speed are employed. Using the HHNEC 0.25μm CMOS technology, area of the design is about 48(kilo) equivalent gates and its system frequency is up to 70MHz. The through put of the 128bit data encryption and decryption is as high as 380Mbps.