ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2019, Vol. 56 ›› Issue (12): 2733-2743.doi: 10.7544/issn1000-1239.2019.20180267

• 系统结构 • 上一篇    



  1. 1(北京大学工学院 北京 100871);2(清华大学计算机系 北京 100084);3(北京信息科学与技术国家研究中心(清华大学) 北京 100084) (
  • 出版日期: 2019-12-01
  • 基金资助: 

Extending PCM Lifetime by Redirecting Writes from the Most Modified Byte

Gao Peng1, Wang Dongsheng2, Wang Haixia3   

  1. 1(College of Engineering, Peking University, Beijing 100871);2(Department of Computer Science and Technology, Tsinghua University, Beijing 100084);3(National Research Center for Information Science and Technology (Tsinghua University), Beijing 100084)
  • Online: 2019-12-01

摘要: 现代存储系统一般是由多个存储芯片通过并列数据线、共享地址线的方式构成的.因此,在多片相变存储芯片并联构成的内存系统中,如果多个芯片间的磨损存在较大差异,那么该系统的寿命将会因短板效应而受到影响.模拟实验和数据分析均确认了这一问题在实际系统中的存在.在此基础上,提出了一种混合内存设计,用于延长相变内存的寿命.该方法引入了一种动态识别机制,可以在每次写入时识别遭受最多磨损的相变存储芯片,并将该芯片未来的写入转移到另一个长寿命的存储芯片中.这一措施可以减少对相变存储芯片的总写入量,并缩小相变存储芯片间的写入量差别.实验表明:使用RMB设计的内存系统的寿命最多可达无任何寿命延长方法时的7.9倍,可达使用经典方法PRES的5.14倍.

关键词: 相变存储器, 片间磨损局部性, 写减少算法, 磨损均衡算法, 混合内存

Abstract: Structure of recent memory system is always comprised of multiple memory chips, where it concatenates data lines of each chip, and shares the address lines. Consequently, the service time of such a memory system, especially built by the write sensitive memory device such PCM, could be diminished due to the bucket effect. Specifically, it means that some storage chips are wearing faster than others because of writing difference among storage chips. So, the present work first proves the existence of bucket effect by numerical experiment and data analysis. Then, a hybrid memory design method termed RMB (redirecting the most-modified byte) is proposed to prolong the endurance of the PCM based memory system. Along with PCM chips, the system works with an additional long-life auxiliary chip to that whose writing can be redirected from any PCM chip with more modified times than the other chips. The method comes with following two advantages simultaneously: the wearing of the most modified chip as well as that of all PCM chips are reduced, and the writing differences among all PCM chips are balanced. The evaluations prove that it successfully enhances the endurance of the memory system at most 7.9x than the memory without wear mitigating technique, and at most 5.14x than the state-of-the-art technique PRES.

Key words: phase change memory, inter-chip wearing locality, write-reduction, wear-levelling, hybrid memory