ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2022, Vol. 59 ›› Issue (3): 499-517.doi: 10.7544/issn1000-1239.20210565

所属专题: 2022存储系统与智能处理专题

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  1. (华中科技大学武汉光电国家研究中心 武汉 430074) (
  • 出版日期: 2022-03-07
  • 基金资助: 

A Scalable Timestamp-Based Durable Software Transactional Memory

Liu Chaojie, Wang Fang, Zou Xiaomin, Feng Dan   

  1. (Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074)
  • Online: 2022-03-07
  • Supported by: 
    This work was supported by the National Key Research and Development Program of China (2018YFB1003305), the Key Program of the National Natural Science Foundation of China (61832020), and the Foundation for Innovative Research Groups of the National Natural Science Foundation of China (61821003).

摘要: 新兴的非易失性内存(non-volatile memory, NVM)具有字节寻址、持久性、大容量和低功耗等优点,然而,在NVM上进行并发编程往往比较困难,用户既要保证数据的崩溃一致性又要保证并发的正确性.为了降低用户开发难度,研究人员提出持久性事务内存方案,但是现有持久性事务内存普遍存在扩展性较差问题.测试发现限制扩展性的关键因素在于全局逻辑时钟和冗余NVM写操作.针对这2个方面,提出了线程逻辑时钟方法,通过允许每个线程拥有一个独立时钟,消除全局逻辑时钟中心化问题;提出了缓存行感知的双版本方法,为数据维护2个版本,通过循环更新这2个版本来保证数据的崩溃一致性,从而消除冗余的NVM写操作.基于所提出的这2个方法,实现了一个基于时间戳的高扩展的持久性软件事务内存(scalable durable transactional memory, SDTM),对比测试显示,在YCSB负载下,与DudeTM和PMDK相比,SDTM的性能最多分别提高了2.8倍和29倍.

关键词: 持久性事务内存, 并发控制, 非易失性内存, 数据一致性, ACID特性

Abstract: The emerging non-volatile memory(NVM) provides a lot of advantages, including byte-addressability, durability, large capacity and low energy consumption. However, it is difficult to perform concurrent programming on NVM, because users have to ensure not only the crash consistency but also the correctness of concurrency. In order to reduce the development difficulty, persistent transactional memory has been proposed, but most of the existing persistent transactional memory has poor scalability. Through testing, we find that the limiting factors of scalability are global logical clock and redundant NVM write operation. In order to eliminate the impact of these two factors on scalability: A thread logical clock method is proposed, which eliminates the problem of global logical clock centralization by allowing each thread to have an independent clock; a dual version method of cache line awareness is proposed, which maintains two versions of the data, and updates the two versions cyclically to ensure the crash consistency of the data, thereby eliminating redundant NVM write operations. And based on these two methods, a scalable durable transactional memory (SDTM) is implemented and fully tested. The results show that under YCSB workload, compared with DudeTM and PMDK, its performance is up to 2.8 times and 29 times higher, respectively.

Key words: durable transactional memory (DTM), concurrent control, non-volatile memory (NVM), data consistency, properties of atomicity, consistency, isolation, and durability (ACID properties)