Abstract: IEEE 802.15.3c is international unified standard of high-rate wireless personal area networks (high-rate WPANs) to support high data rate applications such as high-definition streaming content downloads, home theater and etc, which needs to finish 512 FFT sizes operations in only 222.2ns at the sampling rate of 2.592GHz. To satisfy this demand, some FFT processors adopt parallel PEs and reformulated radix-2\+4 FFT algorithm which can reduce the required number of butterfly stages. When parallel PEs are employed, only memory system supporting these PEs parallel accessing operating data and normal order I/O can express the full advantages of parallel PEs. According to the accessing law of four reformulated radix-2\+4 FFT PEs, this paper designs an address transformation method supporting four reformulated radix-2\+4. And the method in this paper supports normal order I/O, which solves the difficulty caused by bit reversal operation of initial or result data, to get a high-throughput design result. The implementation of the single address transformation unit is simple which requires only three two-input XOR gates and one three-input XOR gate. At the same synthesis condition, this method saves area 47% and power 24% compared with the method before. And this method supports continuous flow and in-place operation.

Key words: IEEE 802.15.3c, radix-2\+4, FFT, address schedule, parallel, in-place, continuous-flow