ISSN 1000-1239 CN 11-1777/TP

Journal of Computer Research and Development ›› 2017, Vol. 54 ›› Issue (5): 1077-1085.doi: 10.7544/issn1000-1239.2017.20160122

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Optimizing and Implementing the High Dynamic Range Video Algorithom

Wu An1, Jin Xi1,2, Du Xueliang2, Zhang Kening1, Yao Chunhe1, Ma Shufen2   

  1. 1(Key Laboratory of Strongly-Coupled Quantum Matter Physics (School of Physical Sciences, University of Science and Technology of China), Chinese Academy of Sciences, Hefei 230026); 2(Hefei Branch Center of National ASIC Design Engineering Technology Research Center, Hefei 230026)
  • Online:2017-05-01

Abstract: In contrast to the HDR image processing algorithm, the computation complexity of HDR video processing algorithm make the hardware implementation consume much more logics and storage resources, which poses an enormous obstacle for the existing algorithms to achieve real-time processing. As a consequence, a new algorithm for real-time hardware implementation is demanded. In this paper, we propose a fully pipelined hardware system processing HDR video in real-time, which takes advantage of parallel configurable characteristics of FPGA. Our system obtains a series of low dynamic range (LDR) images adopting varying exposure time algorithm and places their camera response curves in the FPGA look-up table (LUT). Then the translated float data is stored in the BRAM or FIFO modules in parallel pipeline. Finally, the image is displayed in the device by adopting rapid global Tone Mapping algorithm. The entire HDR video processing system is realized in Xilinx Kintex-7 FPGA board. Results show that the processing efficiency can reach 65 f/s for the 1 920×1 080 resolution video when the system clock rate is 120 MHz, which is sufficient for the real-time processing requirements.

Key words: FPGA, high dynamic range video (HDR), tone mapping, comparametric camera response function LUT (CCRF LUT), radiance map

CLC Number: