ISSN 1000-1239 CN 11-1777/TP

Journal of Computer Research and Development ›› 2018, Vol. 55 ›› Issue (2): 265-272.doi: 10.7544/issn1000-1239.2018.20170695

Special Issue: 2018面向新型硬件的数据管理专题

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Design and Verification of NVM Control Architecture Based on High-Performance SOC FPGA Array

Liu Ke, Cai Xiaojun, Zhang Zhiyong, Zhao Mengying, Jia Zhiping   

  1. (School of Computer Science and Technology, Shandong University, Qingdao, Shandong 262000)
  • Online:2018-02-01

Abstract: Emerging non-volatile memory (NVM) technologies are getting mature with lower latency and higher bandwidth. In the future, these new technologies show the potentials that not only replace the DRAM as the main memory but also serve in the external memory storage. Meanwhile, designing an efficient memory system has become popular in both the academic world and the industrial world. In this paper, we describe a high-performance NVM verification architecture based on the array of SOC FPGAs. Within the architecture, multiple levels of FPGAs are employed to connect many NVMs. Based on the architecture, we propose a novel master-slave NVM controller and then design a hardware prototype accordingly. The experiment results running on this prototype show that the architecture can not only test the performance of the homogenous NVM groups, but also verify the management scheme of hybrid NVM arrays. Moreover, the high performance of MRAM shows that MRAM has the potential to serve in both cache and main memory.

Key words: non-volatile memory (NVM), FPGA array, hybrid memory, memory controller, SOC FPGA

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