Abstract: Structure of recent memory system is always comprised of multiple memory chips, where it concatenates data lines of each chip, and shares the address lines. Consequently, the service time of such a memory system, especially built by the write sensitive memory device such PCM, could be diminished due to the bucket effect. Specifically, it means that some storage chips are wearing faster than others because of writing difference among storage chips. So, the present work first proves the existence of bucket effect by numerical experiment and data analysis. Then, a hybrid memory design method termed RMB (redirecting the most-modified byte) is proposed to prolong the endurance of the PCM based memory system. Along with PCM chips, the system works with an additional long-life auxiliary chip to that whose writing can be redirected from any PCM chip with more modified times than the other chips. The method comes with following two advantages simultaneously: the wearing of the most modified chip as well as that of all PCM chips are reduced, and the writing differences among all PCM chips are balanced. The evaluations prove that it successfully enhances the endurance of the memory system at most 7.9x than the memory without wear mitigating technique, and at most 5.14x than the state-of-the-art technique PRES.

Key words: phase change memory, inter-chip wearing locality, write-reduction, wear-levelling, hybrid memory