[1] |
Qu Peng, Chen Jiajie, Zhang Youhui, Zheng Weimin.
A Proposal of Software-Hardware Decoupling Hardware Design Method for Brain-Inspired Computing
[J]. Journal of Computer Research and Development, 2021, 58(6): 1146-1154.
|
[2] |
Yan Mingyu, Li Han, Deng Lei, Hu Xing, Ye Xiaochun, Zhang Zhimin, Fan Dongrui, Xie Yuan.
A Survey on Graph Processing Accelerators
[J]. Journal of Computer Research and Development, 2021, 58(4): 862-887.
|
[3] |
Li Xiaobo, Tang Zhimin, Li Wen.
FPGA Verification for Heterogeneous Multi-Core Processor
[J]. Journal of Computer Research and Development, 2021, 58(12): 2684-2695.
|
[4] |
Yang Xiangrui, Yan Jinli, Chen Bo, Peng Jintao, Li Junshuai, Quan Wei, Sun Zhigang.
FlexTSN: A Flexible TSN Switch Implementation Model
[J]. Journal of Computer Research and Development, 2021, 58(1): 153-163.
|
[5] |
Guo Jinyang, Shao Chuanming, Wang Jing, Li Chao, Zhu Haojin, Guo Minyi.
Programming and Developing Environment for FPGA Graph Processing: Survey and Exploration
[J]. Journal of Computer Research and Development, 2020, 57(6): 1164-1178.
|
[6] |
Ou Yan, Feng Yujing, Li Wenming, Ye Xiaochun, Wang Da, Fan Dongrui.
Optimum Research on Inner-Inst Memory Access Conflict for Dataflow Architecture
[J]. Journal of Computer Research and Development, 2019, 56(12): 2720-2732.
|
[7] |
Han Dong, Zhou Shengyuan, Zhi Tian, Chen Yunji, Chen Tianshi.
A Survey of Artificial Intelligence Chip
[J]. Journal of Computer Research and Development, 2019, 56(1): 7-22.
|
[8] |
Li Junnan, Yang Xiangrui, Sun Zhigang.
DrawerPipe: A Reconfigurable Packet Processing Pipeline for FPGA
[J]. Journal of Computer Research and Development, 2018, 55(4): 717-728.
|
[9] |
Lu Ye, Chen Yao, Li Tao, Cai Ruichu, Gong Xiaoli.
Convolutional Neural Network Construction Method for Embedded FPGAs Oriented Edge Computing
[J]. Journal of Computer Research and Development, 2018, 55(3): 551-562.
|
[10] |
Liu Ke, Cai Xiaojun, Zhang Zhiyong, Zhao Mengying, Jia Zhiping.
Design and Verification of NVM Control Architecture Based on High-Performance SOC FPGA Array
[J]. Journal of Computer Research and Development, 2018, 55(2): 265-272.
|
[11] |
Wu An, Jin Xi, Du Xueliang, Zhang Kening, Yao Chunhe, Ma Shufen.
Optimizing and Implementing the High Dynamic Range Video Algorithom
[J]. Journal of Computer Research and Development, 2017, 54(5): 1077-1085.
|
[12] |
Tang Wen,Zhang Chunming,Tan Guangming,Zhang Peiheng,Sun Ninghui.
A Customized Coprocessor Acceleration of Genome Re-Sequencing
[J]. Journal of Computer Research and Development, 2014, 51(9): 1980-1992.
|
[13] |
Xia Jing1,2,3, Wang Tiancheng2, Lü Tao2, Li Huawei2, Kuang Jishun1.
SER-Tvpack: An SER Estimation-Based Clustering Method for SRAM-Based FPGAs
[J]. 计算机研究与发展, 2014, 51(8): 1764-1772.
|
[14] |
Zhu Ying, Chen Cheng, Xu Xiaohong, and Li Yanzhe.
Design and Implementation of FPGA Verification Platform for Multi-core Processor
[J]. Journal of Computer Research and Development, 2014, 51(6): 1295-1303.
|
[15] |
Liu Xingkui, Shao Zongyou,, Liu Xinchun, and Sun Ninghui.
Fine-Grained Parallel Regular Expression Matching for Deep Packet Inspection
[J]. Journal of Computer Research and Development, 2014, 51(5): 1061-1070.
|