Advanced Search
    He Weifeng, Mao Zhigang, Lü Zhiqiang, and Yin Haifeng. VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor[J]. Journal of Computer Research and Development, 2005, 42(7): 1225-1230.
    Citation: He Weifeng, Mao Zhigang, Lü Zhiqiang, and Yin Haifeng. VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor[J]. Journal of Computer Research and Development, 2005, 42(7): 1225-1230.

    VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor

    • An improved architecture for motion estimation using the full-search block-matching algorithm is proposed in this paper. To reduce the utilization of the global bus to the external memory and to improve the data reuse efficiency of search frame pixels, a multi-port matching scheme and double clock strategy are adopted. Compared with the previous FBMA architecture, this new architecture achieves 74.9% processor utilization as well as improves the reuse efficiency of search area pixel data. The motion estimation processor is implemented using the TSMC 0.25μm 1-poly 5-metal CMOS technology, which occupies a silicon area of 3.37mm×3.37mm and operates at 110MHz. Experimental results show that it is able to estimate full pixel motion vectors of MPEG-4 AS profile sequences in ITU-R601 format (720×480@30Hz/NTSC or 720×576@25Hz/PAL) in real-time at around 89.4MHz
    • loading

    Catalog

      Turn off MathJax
      Article Contents

      /

      DownLoad:  Full-Size Img  PowerPoint
      Return
      Return