Test Response Compactor for Scan-Based Circuit

A novel sequential compactor called Awl-compactor is presented to compact the response data during testing. The proposed Awl-compactor can be embedded in the circuit as a kind of on-chip test resource. Due to the single output, the best compaction ratio can be obtained by the Awl-compactor. Based on the distribution analysis of error bits during scan test, the two design rules will be proposed to avoid 2, 3 and any odd errors cancellation, including not only the static error bits cancellation but also the dynamic error bits cancellations. These two rules can also be used to handle the masking of unknown bits in response data. One error bit with one unknown bit should be detected if the two proposed rules are satisfied. In order to generate the register transfer level design or gate netlist design of the compactor automatically in the conventional design flow, a synthesis algorithm based on random selection is presented. Some experiments on the analysis of area overhead and error bits cancellations are conducted. The experimental data shows that the proposed compactor can obtain the maximum compaction ratio and advanced performance only with small area overhead penalty compared to the previous techniques.