A High Level Synthesis Scheme and Its Realization for Low Power Design in VLSI

Power consumption is one of the most important problems used in electronic systems today. High level synthesis can quickly trade off different objectives for complex designs during architecture optimization. A design at high level synthesis in VLSI includes two important tasks: scheduling and interconnection. In order to lower power in design, the two aspects can be considered simultaneously. In this paper, a high level synthesis scheme based on multiple voltages is proposed for low power design in VLSI under the timing and the resource constraints. In this scheme both scheduling and interconnection are considered to reduce power. First, for a given control and data flow graph, scheduling is done in Gain. Then the buses are allocated by interconnection consumption. The register transfer level graph can be optimized by the scheme in the end. In Gain scheduling, the priority function includes the power gain, the mobility, and the computation density of an operation which are three main factors in VLSI design. In interconnection, the transition activities on the signal lines and the coupling capacitances of the lines are considered simultaneously based on RS model. This scheme is implemented in CDFG Toolkits. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.