A Two-Dimensional Parity-Based Concurrent Error Detection Method for AES Against Differential Fault Attack and Its VLSI Implementation

A two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack is proposed. It combines two traditional one dimension parity check methods together to check errors in two directions. A simulation has been conducted to compare the fault coverage of the method in this paper with that of traditional parity-based CED methods. Compared with previous parity-based CED methods, this scheme has a more optimized configuration in choosing the number and position of the parity-check bits. This approach is able to detect odd-bits errors in both horizontal and vertical direction. Therefore it has much higher coverage over multi-bits errors while keeping 100% coverage over odd-bits errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, a pipelined structure is adopted and all parity calculation modules are reusable in both horizontal and vertical parity calculations. The hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than that of the traditional methods, whereas the critical path and throughput of this approach remain the same as that of traditional ways. This is a novel CED method for AES algorithm against differential fault attack because of its high efficiency and low cost.