Decoded Instruction Cache for Reducing Startup Overhead in Co-Designed Virtual Machines

Co-designed virtual machines (co-VM) provide the processor designer with new opportunities for innovation through the combined hardware and software. Co-VM uses dynamic binary translation to implement binary compatibility between different instruction set architectures (ISA). Interpreting and translating the source ISA binaries will affect the startup performance of a co-VM. In the exploration of startup performance of our VM which employs interpretation and superblock translation, we observe that the cold code interpretation causes the major startup overhead of co-VM and the redundant source instruction decoding forms the bottleneck of interpretation. We oberserve the interpretation routine locality and propose a hardware decoded instruction cache (DICache) for saving instruction information decoded during interpretation. DICache can be organized as normal cache and maintained by hardware. We implement a co-VM and conduct some benchmarks from SYSmark 2004 SE to evaluate the DICache performance on a co-VM. We also evaluate the implementation overhead of DICache, such as area and power consumption. It is demonstrated that DICache could significantly reduce the redecoding operations and speedup the interpretation, thus bringing a speedup of 2.4 on average relative to the startup performance of the normal co-VM. Compared with other related optimization techniques, DICache performs more efficiently with better adaptability.