Research on FPGA-Based Paging-Simulation Model for SIMD Architecture

With the appearance of massively compute-intensive applications such as multimedia and complicated scientific computing, SIMD architecture has become a hotspot of research due to its intrinsic scalable data-parallel structure. The low simulating speed of software simulation brings lots of inconveniency in large scale SMID architecture research. FPGA-based simulation system is much faster, but the scale of the target system is often limited by the capacity of the FPGA chips. Using more FPGA chips or larger capacity FPGA chip may not only increase the complexity of design, but also increase the cost of research. In this paper, we propose a novel FPGA-based paging-simulation model for SIMD architecture, which can reduce the computing resource and memory resource consuming of the simulation system efficiently. On the basis of this model, large scale SIMD architectures can be simulated with limited FPGA resources. We build the simulation system of MASA on Altera StratixII series chip EP2S180. The experiment results show that without any simulation optimizing technology, the largest scale system can be implemented on EP2S180 is MASA of 8 clusters, while based on the paging-simulation model, the largest scale system can be implemented on EP2S180 with MASA of 256 clusters, and the increment of the simulation time is acceptable.