A Parallel Architecture for FPGA Based Hyperelliptic Curve Cryptoprocessor

Hyperelliptic curve is an extension of elliptic curve cryptography. Shorter key lengths of hyperellitic curve cryptosystems (HECC) can be used to achieve same level of security comparing to RSA and elliptic curve cryptosystem (ECC). A parallel architecture for field programmable gate array (FPGA) based hyperelliptic curve cryptoprocessor is designed in this paper. The processor is composed of parallel finite field (FF) cores, and each core consists of a control unit, a register file and an ALU. Through sharing mechanism of register files, the independent cores can collaborate to fulfill complicated computations. Each ALU can execute customized instruction A(B+C)+D, and the instruction can be flexibly configured in the instruction generation and execution process. In our architecture, since every ALU is coupled with a control unit and a ROM, the ALUs are independent of each other. Any ALU can be started at any cycle, so multiple instructions can run on ALUs at the same time. The results of ALUs can be shared among the register files, so multiple ALUs can cooperate to finish complicated computations. A four stage pipeline is used to increase performance. The architecture designed can sufficiently support parallel processing and much higher speed up has been gained with the experiment results.