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    Feng Chaochao, Zhang Minxuan, Li Jinwen, and Dai Yi. A Fault-Tolerant Deflection Router with Reconfigurable Bidirectional Link for NoC[J]. Journal of Computer Research and Development, 2014, 51(2): 454-463.
    Citation: Feng Chaochao, Zhang Minxuan, Li Jinwen, and Dai Yi. A Fault-Tolerant Deflection Router with Reconfigurable Bidirectional Link for NoC[J]. Journal of Computer Research and Development, 2014, 51(2): 454-463.

    A Fault-Tolerant Deflection Router with Reconfigurable Bidirectional Link for NoC

    • With the CMOS technology scaling down to the nanometer domain, continuing decrease in the feature size of integrated circuits leads to the increase in susceptibility to transient and permanent faults. Supporting fault-tolerance in NoC is highly important for the reliable data transmission on chip-multiprocessors. A fault-tolerant deflection router with reconfigurable bidirectional link for NoC (called BiFTDR) is proposed to protect against transient and permanent faulty links. A pair of reconfigurable bidirectional links connect two neighboring BiFTDR routers. The direction of the bidirectional links can be reconfigured dynamically according to the fault status of the link and the information of the arriving packets. The BiFTDR router can achieve fault-tolerance without misrouting in the case of unidirectional link faults. In addition, the router does not need the routing table, which can reduce the hardware overhead significantly. Simulation results illustrate that in synthetic traffic patterns, the BiFTDR router achieves 10% and 19% less average latency than a reinforcement-learning-based fault-tolerant deflection router under 5 and 15 permanent faulty links respectively. In the real application traffic workloads, compared with the average latency of the network without faulty links, the performance degradation of the BiFTDR router is less than 1%. For transient faults, the performance of the BiFTDR router can achieve graceful degradation even at a high fault rate. The BiFTDR router is synthesized in 65nm technology, and is shown to achieve the frequency of 500MHz with smaller area and power consumption overhead.
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