ISSN 1000-1239 CN 11-1777/TP

Journal of Computer Research and Development ›› 2016, Vol. 53 ›› Issue (2): 341-353.doi: 10.7544/issn1000-1239.2016.20148436

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A Lightweight Fine-Grained Fault-Tolerant Scheme for 3D Networks-on-Chip

Zhou Jun1,2, Li Huawei1, Wang Tiancheng1,2, Li Xiaowei1   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190); 2(University of Chinese Academy of Sciences, Beijing 100049)
  • Online:2016-02-01

Abstract: 3D network-on-chip (NoC) is one of the main trends of the communication technology for 3D integrated circuits (ICs). Each processing element (PE) in the networks communicates with its attached router node through the network interface (NI), and different nodes are connected to their neighbors with the horizontal or vertical links. With the increase of complexity and integration level, the interference to the communication of NoCs becomes more and more serious, and the probability of fault occurrence also rises up. In order to guarantee the normal operation of the circuits, effective fault-tolerant schemes need to be designed for the networks. The routers are one of the main components of NoCs. For most of the existing fault-tolerant schemes, faulty routers are usually completely replaced by the redundant ones or even deprecated. In this paper, we propose a lightweight fine-grained fault-tolerant scheme to take full advantage of the remaining valid resources of the routers in 3D NoCs. Our scheme includes a new reliable micro-architecture designed for the routers and a matching lightweight fault-tolerant routing scheme. Experimental results show that the proposed scheme possesses higher performance, improved reliability and lower overhead compared with the state-of-the-art fault-tolerant schemes for 3D NoCs.

Key words: networks-on-chip, 3D mesh, fine-granularity, fault-tolerance, routing scheme

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