[1] |
He Ximing, Ma Sheng, Huang Libo, Chen Wei, Wang Zhiying.
A Simple and Efficient Cache Coherence Protocol Based on Self-Updating
[J]. Journal of Computer Research and Development, 2019, 56(4): 719-729.
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[2] |
Zhang Dongsong, Wang Jue, Zhao Zhifeng, Wu Fei.
PLUFS: An Overhead-Aware Online Energy-Efficient Scheduling Algorithm for Periodic Real-Time Tasks in Multiprocessor Systems
[J]. Journal of Computer Research and Development, 2016, 53(7): 1454-1466.
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[3] |
Zhu Suxia, Chen Deyun, Ji Zhenzhou, Sun Guanglu, Zhang Hao.
A Concurrent Memory Race Recording Algorithm for Snoop-Based Coherence
[J]. Journal of Computer Research and Development, 2016, 53(6): 1238-1248.
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[4] |
Peng Hao, Han Jianghong, Lu Yang, Zhang Jianjun.
Multiprocessor Hard Real-Time Systems Preemption Threshold Scheduling
[J]. Journal of Computer Research and Development, 2015, 52(5): 1177-1186.
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[5] |
Wang Yizhuo, Zuo Qi, Ji Weixing, Wang Xiaojun, Shi Feng.
Memory-Aware Incremental Mapping of Applications to MPSoC
[J]. Journal of Computer Research and Development, 2015, 52(5): 1198-1209.
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[6] |
Zhu Suxia, Ji Zhenzhou, Li Dong, and Zhang Hao.
A Cyclic Memory Race Recording Algorithm Implemented with Hardware Signatures
[J]. Journal of Computer Research and Development, 2014, 51(5): 1149-1157.
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[7] |
Lü Fang, Cui Huimin, Huo Wei, and Feng Xiaobing.
Survey of Scheduling Policies for Co-Run Degradation
[J]. Journal of Computer Research and Development, 2014, 51(1): 17-30.
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[8] |
Ding Wanfu, Guo Ruifeng, Qin Chenggang, and Guo Fengzhao,.
A Fault-Tolerant Scheduling Algorithm with Software Fault Tolerance in Hard Real-Time Systems
[J]. , 2011, 48(4): 691-698.
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[9] |
Wang Wei, Qiao Lin, Yang Guangwen, and Tang Zhizhong.
Performance Analysis of the 2-D Networks-On-Chip for Local Uniform Random Communication Pattern
[J]. , 2010, 47(3): 532-540.
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[10] |
Wu Wei, Ni Shaojie, and Wang Feixue.
A Fault-Tolerant Scheduling Method Based on Predictable Deadline Miss Ratio in High Utilization
[J]. , 2010, 47(2): 370-376.
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[11] |
Wang Wei, Qiao Lin, Yang Guangwen, and Tang Zhizhong.
Performance Analysis of the 2-D Networks-on-Chip
[J]. , 2009, 46(10): 1601-1611.
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[12] |
Xiao Junhua, Feng Zijun, and Zhang Longbing.
The Tradeoff Cache Between Latency and Capacity in Chip Multiprocessors
[J]. , 2009, 46(1): 167-175.
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[13] |
Li Renfa, Liu Yan, and Xu Cheng.
A Survey of Task Scheduling Research Progress on Multiprocessor System-on-Chip
[J]. , 2008, 45(9): 1620-1629.
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[14] |
Gao Xiang, Zhang Longbing , and Hu Weiwu.
A CapacityShared Heterogeneous CMP Cache
[J]. , 2008, 45(5): 877-885.
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[15] |
Zhao Mingyu and Zhang Tianwen.
DAG Scheduling for Synchronous Communication in the Network Computing Environment
[J]. , 2008, 45(4): 695-705.
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