ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2016, Vol. 53 ›› Issue (2): 341-353.doi: 10.7544/issn1000-1239.2016.20148436

• 系统结构 • 上一篇    下一篇

面向3维片上网络的轻量级细粒度容错机制

周君1,2,李华伟1,王天成1,2,李晓维1   

  1. 1(计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京 100190); 2(中国科学院大学 北京 100049) (zhoujun@ict.ac.cn)
  • 出版日期: 2016-02-01
  • 基金资助: 
    国家自然科学基金项目(61432017,61176040,61221062);国家“九七三”重点基础研究发展规划基金项目(2011CB302501)

A Lightweight Fine-Grained Fault-Tolerant Scheme for 3D Networks-on-Chip

Zhou Jun1,2, Li Huawei1, Wang Tiancheng1,2, Li Xiaowei1   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190); 2(University of Chinese Academy of Sciences, Beijing 100049)
  • Online: 2016-02-01

摘要: 片上网络(networks-on-chip, NoC)是3维集成电路的主要通信技术之一.其中,路由器是3维片上网络的重要组成部件.现有的面向3维片上网络中路由器的容错技术,通常采取路由器整体冗余技术或者直接舍弃失效路由器的方法,这导致网络资源损失较为严重.提出一种面向3维片上网络的轻量级细粒度容错机制,充分利用故障路由器中仍能正常运行的有效资源,保障系统通信.提出的容错机制包括一种高可靠性路由器微体系结构设计和一种与之匹配的容错路由机制.通过实验对比和分析,相比较于已有的3维片上网络容错机制,提出的细粒度容错机制具备较高的通信性能和可靠性,同时面积和功耗开销较小.

关键词: 片上网络, 3维mesh, 细粒度, 容错, 路由机制

Abstract: 3D network-on-chip (NoC) is one of the main trends of the communication technology for 3D integrated circuits (ICs). Each processing element (PE) in the networks communicates with its attached router node through the network interface (NI), and different nodes are connected to their neighbors with the horizontal or vertical links. With the increase of complexity and integration level, the interference to the communication of NoCs becomes more and more serious, and the probability of fault occurrence also rises up. In order to guarantee the normal operation of the circuits, effective fault-tolerant schemes need to be designed for the networks. The routers are one of the main components of NoCs. For most of the existing fault-tolerant schemes, faulty routers are usually completely replaced by the redundant ones or even deprecated. In this paper, we propose a lightweight fine-grained fault-tolerant scheme to take full advantage of the remaining valid resources of the routers in 3D NoCs. Our scheme includes a new reliable micro-architecture designed for the routers and a matching lightweight fault-tolerant routing scheme. Experimental results show that the proposed scheme possesses higher performance, improved reliability and lower overhead compared with the state-of-the-art fault-tolerant schemes for 3D NoCs.

Key words: networks-on-chip, 3D mesh, fine-granularity, fault-tolerance, routing scheme

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