ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2016, Vol. 53 ›› Issue (7): 1447-1453.doi: 10.7544/issn1000-1239.2016.20160150

所属专题: 2016绿色计算专题

• 系统结构 • 上一篇    下一篇

基于SMART技术的片上网络低功耗策略P-SMART

李彬,董德尊,吴际,夏军   

  1. (国防科学技术大学计算机学院 长沙 410073) (xtlil3@163.com)
  • 出版日期: 2016-07-01
  • 基金资助: 
    国家自然科学基金项目(61272482);全国百篇优秀博士论文基金项目(201450);教育部高等学校博士学科点专项科研基金项目(20124307120026)

P-SMART: An Energy-Efficient NoC Router Based on SMART

Li Bin, Dong Dezun, Wu Ji, Xia Jun   

  1. (College of Computer, National University of Defense Technology, Changsha 410073)
  • Online: 2016-07-01

摘要: 片上网络(network-on-chip, NoC)消耗的功耗在整个芯片中所占比例不断增大,并且随着芯片工艺精度的提升和工作电压的不断降低,静态功耗占片上网络总功耗的比例也越来越大.当前芯片设计者致力于将未被使用的核设置为休眠状态来降低功耗.然而,即便是最前沿的芯片设计,当核休眠时与它连接的路由器都是保持在正常状态来进行报文传输.而与休眠核相连的片上网络路由器由于没有注入和吸收的报文,负载相对较低.在SMART(single-cycle multi-hop asynchronous repeated traversal)片上网络中,报文能够单周期从源路由器到目标路由器.基于单周期多跳旁路(SMART)技术,提出一种关闭低负载路由器虚通道的策略P-SMART,以在不影响网络性能的情况下节省片上网络功耗.实验结果表明:相对于SMART技术,P-SMART的性能损失不超过2%,而功耗节省13.4%.

关键词: 片上互连网络, 功耗, 旁路, 延迟, 虚通道

Abstract: As the number of on-chip cores in chip multiprocessors (CMPs) increase, size of network-on-chips (NoCs) and network latency increase. NoCs consume an increasing fraction of the chip power as technology and voltage continue to scale down, and static power consumes a larger fraction of the total power. Currently, processor designers strive to send under-utilized cores into deep sleep states in order to improve overall energy efficiency. However, even in state-of-the-art CMP designs, when a core going to sleep the router attached to it remains active in order to continue packet forwarding. The router attached to a sleeping core has low traffic load, due to no packets to or from sleeping core. An on-chip network called SMART (single-cycle multi-hop asynchronous repeated traversal) that aims to present a single-cycle data-path all the way from the source to the destination. This paper, we propose reducing the VC(virtual channel) of router that is attached to sleeping core, based on SMART NoC, reducing power consumption and bringing little performance penalty. We evaluate our network using synthetic traffics. Our evaluation results show that VC power gating increases network latency less than 2% when the workload is low, and compared with no bypass path network, the power is reduced about 13.4%.

Key words: network-on-chip (NoC), power consumption, bypass path, latency, virtual channel

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