Abstract: Parallel bit extraction and rotation-shift operations can be completed by bit level permutation. At present, they are mainly implemented independently, which results in the waste of hardware logic resources. Although some of the researches unified the two operations into a single hardware unit, it was required to design two dedicated circuits to implement the routing algorithms for each operation. Consequently, the consumption of the logic resources is still high. To solve this problem, a unified routing algorithm is proposed by studying the mapping principle of rotation-shift and parallel bit extraction operations based on one kind of dynamic multistage interconnect network named Inverse Butterfly Network. The algorithm utilizes the self-routing and recursive characteristics of the network. It not only has high parallelism, but also is simple in hardware implementation, which is conductive to integration for the general-propose processor architecture. On this basis, we also develop a reconfigurable parallel bit extraction hardware unit with rotation-shift function named RPRU, and optimize the critical path of the unit. Then, we synthesize it into CMOS 90nm process. The experimental results show that the area of our RPRU using the unified algorithm is less by 30% than that of the previous design with identical functions.