ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2020, Vol. 57 ›› Issue (6): 1164-1178.doi: 10.7544/issn1000-1239.2020.20200106

所属专题: 2020计算机体系结构前沿技术专题

• 系统结构 • 上一篇    下一篇



  1. (上海交通大学电子信息与电气工程学院 上海 200240) (
  • 出版日期: 2020-06-01
  • 基金资助: 

Programming and Developing Environment for FPGA Graph Processing: Survey and Exploration

Guo Jinyang, Shao Chuanming, Wang Jing, Li Chao, Zhu Haojin, Guo Minyi   

  1. (School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240)
  • Online: 2020-06-01
  • Supported by: 
    This work was supported by the National Key Research and Development Plan of China (2018YFB1003500).

摘要: 基于新型可重构架构FPGA(field programmable gate array)的图计算加速器同时具备着性能和能效的优势,满足复杂性高、数据规模大和基本操作多变的图计算的性能需求.但高效底层硬件代码的设计需要很长的设计周期,而已有的通用编程与开发环境虽满足功能要求,但性能差距较大.因此,编程墙的问题是影响应用开发与加速器性能的重要阻碍之一.设计良好的编程与开发环境是图计算加速器进一步提升性能且降低开发周期的最重要环节.高效的编程与开发环境需要提供便利的应用程序接口、扩展性强的编程模型、高效的高层次综合工具、能够融合软硬件特性的领域特定语言以及生成高性能硬件代码.对FPGA图计算的编程与开发环境做出系统性探索,主要就编程模型、高层次综合、编程语言以及应用程序开发进行介绍与分析.此外还对国内外相关技术的发展进行总结与分析,并针对本领域相关开放问题与挑战提供了未来思考.

关键词: 现场可编程门阵列, 图计算, 硬件加速器, 编程与开发环境, 编程模型, 高层次综合, 领域特定语言, 应用程序接口

Abstract: Due to the advantages of high performance and efficiency, graph processing accelerators based on reconfigurable architecture field programmable gate array (FPGA) have attracted much attention, which satisfy complex graph applications with various basic operations and large-scale of graph data. However, efficient code design for FPGA takes long time, while the existing functional programming environment cannot achieve desirable performance. Thus, the problem of programming wall on FPGA is significant, and has become a serious obstacle when designing the dedicated accelerators. A well-designed programming environment is necessary for the further popularity of FPGA-based graph processing accelerators. A well-designed programming environment calls for convenient application programming interfaces, scalable application programming models, efficient high-level synthesis tools, and a domain-specific language that can integrate software/hardware features and generate high-performance underlying code. In this article, we make a systematic exploration of the programming environment for FPGA graph processing. We mainly introduce and analyze programming models, high-level synthesis, programming languages, and the related hardware frameworks. In addition, we also introduce the domestic and foreign development of FPGA-based graph processing accelerators. Finally, we discuss the open issues and challenges in this specific area.

Key words: field programmable gate array (FPGA), graph processing, hardware accelerator, programming environment, programming model, high-level synthesis, domain-specific language, application programming interface (API)