摘要:
近年来，随着摩尔定律逼近极限，片上系统(system on chip, SoC)的发展已经遇到瓶颈.集成更多的功能单元和更大的片上存储使得芯片面积急剧增大，导致芯片良品率降低，进而增加了成本.各大研究机构和芯片制造厂商开始寻求使用先进的连接和封装技术，将原先的芯片拆成多个体积更小、产量更高且更具成本效益的小芯片(Chiplet)再封装起来，这种封装技术类似于芯片的系统级封装(system in package, SiP).目前Chiplet的封装方式没有统一的标准，可行的方案有通过硅桥进行芯片的拼接或是通过中介层进行芯片的连接等，按照封装结构可以分为2D，2.5D，3D.通过归纳整理目前已发布的小芯片产品，讨论了各个结构的优缺点.除此之外，多个小芯片之间的通信结构也是研究的重点，传统的总线或者片上网络(network on chip, NoC)在Chiplet上如何实现，总结遇到的挑战和现有解决方案.最后通过对现有技术的讨论，探索以后小芯片发展的趋势和方向.
Abstract:
In recent years, as Moore’s Law approaches the limit, the development of system on chip (SoC) has encountered bottlenecks. Integrating more functional units and larger on-chip storage makes the chip area increase sharply, resulting in a decrease in chip’s yield, which in turn increases costs. In order to break through the limitations of Moore’s Law, research institutions and chip manufacturers began to seek to use advanced connection and packaging technology to disassemble the original chip into multiple smaller, higher-yielding, and cost-effective Chiplets and then reassemble them. This packaging technology is similar to the system in package (SiP) of the chip. At present, there is no unified standard for the packaging methods of Chiplets, the feasible solutions include chip splicing through silicon bridges or chip connection through interposers, etc., which can be divided into 2D, 2.5D, 3D according to the packaging structure. By summarizing the currently released Chiplets products, we discuss the advantages and disadvantages of each structure. In addition, the communication structure between multiple Chiplets is also the focus of research. How to implement a traditional bus or network on chip (NoC) on Chiplets? This paper explores the development trend and direction of Chiplets in the future through discussion of existing technologies.
百度学术
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