ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2021, Vol. 58 ›› Issue (12): 2684-2695.doi: 10.7544/issn1000-1239.2021.20200289

• 系统结构 • 上一篇    下一篇

面向异构多核处理器的FPGA验证

李小波1,2,3,唐志敏1,2,3,李文3   

  1. 1(计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京 100190);2(中国科学院大学计算机科学与技术学院 北京 100049);3(上海处理器技术创新中心 上海 200120) (lixiaobo17b@ict.ac.cn)
  • 出版日期: 2021-12-01
  • 基金资助: 
    国家重点研发计划项目(2018YFB1003501);国家自然科学基金项目(61732018,61872335);计算机体系结构国家重点实验室开放课题(CARCH201914)

FPGA Verification for Heterogeneous Multi-Core Processor

Li Xiaobo1,2,3, Tang Zhimin1,2,3, Li Wen3   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190);2(School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049);3(Shanghai Processor Technology Innovation Center, Shanghai 200120)
  • Online: 2021-12-01
  • Supported by: 
    This work was supported by the National Key Research and Development Program of China (2018YFB1003501), the National Natural Science Foundation of China (61732018, 61872335), and the Open Program of the State Key Laboratory of Computer Architecture (CARCH201914).

摘要: 随着处理器架构的发展,高性能异构多核处理器不断涌现.由于高性能异构多核处理器的设计十分复杂,为了降低设计风险,缩短验证周期,提前进行软件开发,复现硅后问题等,通常需要搭建现场可编程门阵列(field programmable gate array, FPGA)的原型验证平台,并基于FPGA平台开展种类繁多,功能各异的软硬协同验证和调试工作.提出的基于同构FPGA平台对异构多核高性能处理器的FPGA调试、验证方法,有效地利用了异构多核处理器的架构特征,同构FPGA的对称特点,以层次化的方法自顶向下划分FPGA,自底向上构建FPGA平台.结合差速桥、自适应延迟调节、内嵌的虚拟逻辑分析仪(virtual logic analyzer, VLA)等技术可快速完成FPGA平台的点亮(bring-up)和部署.所提出的多核互补,核间替换模拟的调试SHELL等方法可以快速完整地对目标高性能异构多核处理器进行FPGA验证.通过该FPGA原型验证平台,成功地完成了硅前验证,软硬件协同开发和测试,硅后问题复现工作,并为下一代处理器架构设计提供了快速的硬件平台.

关键词: 异构多核, FPGA原型验证, 差速桥, 自适应延迟调节, 虚拟逻辑分析仪, 核间替换模拟

Abstract: With the development of processor architecture, high-performance heterogeneous multi-core processors are emerging. Since the design of high-performance heterogeneous multi-core processor is very complex, in order to reduce the design risk, shorten the verification cycle, carry out software development in advance, reproduce the post-silicon problems, we usually need to build a prototype verification platform of field programmable gate array (FPGA), and based on the FPGA platform to carry out a variety of software and hardware verification and debugging work with different functions. This paper presents a method of debugging and verifying heterogeneous multi-core high-performance processor based on homogeneous FPGA platform which effectively utilizes the architecture characteristics of heterogeneous multi-core processor and the symmetry characteristics of homogeneous FPGA platform, divides FPGA by hierarchical top down method, builds the platform from bottom to up. The combination of speed bridge, adaptive delay adjustment, embedded virtual logic analyzer and other technologies can quickly complete the FPGA platform bring-up and deployment. The proposed multi-core complementary, inter-core replacement simulation method with debug SHELL can verify the target high-performance heterogeneous multi-core processor quickly and completely. Through the FPGA prototyping platform, we have successfully completed the pre-silicon verification,software hardware co-development and testing, post-silicon bug reproduce and also provided a fast hardware platform for the next generation processor’s architecture design.

Key words: heterogeneous multi-core, field programmable gate array (FPGA) prototyping, speed bridge, adaptive delay adjustment, virtual logic analyzer (VLA), inter-core replacement simulation

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