ISSN 1000-1239 CN 11-1777/TP

计算机研究与发展 ›› 2021, Vol. 58 ›› Issue (6): 1204-1229.doi: 10.7544/issn1000-1239.2021.20210166

所属专题: 2021计算机芯片关键技术前沿与进展专题

• 系统结构 • 上一篇    下一篇

图神经网络加速结构综述

李涵1,2,严明玉1,2,吕征阳1,2,李文明1,叶笑春1,范东睿1,2,唐志敏1,2   

  1. 1(计算机体系结构国家重点实验室(中国科学院计算技术研究所) 北京 100190);2(中国科学院大学 北京 100049) (lihan-ams@ict.ac.cn)
  • 出版日期: 2021-06-01
  • 基金资助: 
    国家自然科学基金项目(61732018,61872335,61802367);中国科学院国际伙伴计划(171111KYSB20200002);数学工程与先进计算国家重点实验室开放基金(2019A07)

Survey on Graph Neural Network Acceleration Architectures

Li Han1,2, Yan Mingyu1,2, Lü Zhengyang1,2, Li Wenming1, Ye Xiaochun1, Fan Dongrui1,2, Tang Zhimin1,2   

  1. 1(State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190);2(University of Chinese Academy of Sciences, Beijing 100049)
  • Online: 2021-06-01
  • Supported by: 
    This work was supported by the National Natural Science Foundation of China (61732018, 61872335, 61802367), the International Partnership Program of Chinese Academy of Sciences(171111KYSB20200002), and the Open Project Program of the State Key Laboratory of Mathematical Engineering and Advanced Computing (2019A07).

摘要: 近年来,新兴的图神经网络因其强大的图学习和推理能力,得到学术界和工业界的广泛关注,被认为是推动人工智能领域迈入“认知智能”阶段的核心力量.图神经网络融合传统图计算和神经网络的执行过程,形成了不规则与规则的计算和访存行为共存的混合执行模式.传统处理器结构设计以及面向图计算和神经网络的加速结构不能同时应对2种对立的执行行为,无法满足图神经网络的加速需求.为解决上述问题,面向图神经网络应用的专用加速结构不断涌现,它们为图神经网络定制计算硬件单元和片上存储层次,优化计算和访存行为,取得了良好的加速效果.以图神经网络执行行为带来的加速结构设计挑战为出发点,从整体结构设计以及计算、片上访存、片外访存层次对该领域的关键优化技术进行详实而系统地分析与介绍.最后还从不同角度对图神经网络加速结构设计的未来方向进行了展望,期望能为该领域的研究人员带来一定的启发.

关键词: 图神经网络, 混合执行模式, 加速结构, 人工智能, 领域专用架构

Abstract: Recently, the emerging graph neural networks (GNNs) have received extensive attention from academia and industry due to the powerful graph learning and reasoning capabilities, and are considered to be the core force that promotes the field of artificial intelligence into the “cognitive intelligence” stage. Since GNNs integrate the execution process of both traditional graph processing and neural network, a hybrid execution pattern naturally exists, which makes irregular and regular computation and memory access behaviors coexist. This execution pattern makes traditional processors and the existing graph processing and neural network acceleration architectures unable to cope with the two opposing execution behaviors at the same time, and cannot meet the acceleration requirements of GNNs. To solve the above problems, acceleration architectures tailored for GNNs continue to emerge. They customize computing hardware units and on-chip storage levels for GNNs, optimize computation and memory access behaviors, and have achieved acceleration effects well. Based on the challenges faced by the GNN acceleration architectures in the design process, this paper systematically analyzes and introduces the overall structure design and the key optimization technologies in this field from computation, on-chip memory access, off-chip memory access respectively. Finally, the future direction of GNN acceleration structure design is prospected from different angles, and it is expected to bring certain inspiration to researchers in this field.

Key words: graph neural network, hybrid execution pattern, acceleration architecture, artificial intelligence, domain-specific architecture

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