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    朱怡安, 史先琛, 姚烨, 李联, 任鹏远, 董威振, 李佳钰. 基于多级一致性协议的多核处理器WCET分析方法[J]. 计算机研究与发展, 2023, 60(1): 30-42. DOI: 10.7544/issn1000-1239.202111244
    引用本文: 朱怡安, 史先琛, 姚烨, 李联, 任鹏远, 董威振, 李佳钰. 基于多级一致性协议的多核处理器WCET分析方法[J]. 计算机研究与发展, 2023, 60(1): 30-42. DOI: 10.7544/issn1000-1239.202111244
    Zhu Yi’an, Shi Xianchen, Yao Ye, Li Lian, Ren Pengyuan, Dong Weizhen, Li Jiayu. A WCET Analysis Method for Multi-Core Processors with Multi-Tier Coherence Protocol[J]. Journal of Computer Research and Development, 2023, 60(1): 30-42. DOI: 10.7544/issn1000-1239.202111244
    Citation: Zhu Yi’an, Shi Xianchen, Yao Ye, Li Lian, Ren Pengyuan, Dong Weizhen, Li Jiayu. A WCET Analysis Method for Multi-Core Processors with Multi-Tier Coherence Protocol[J]. Journal of Computer Research and Development, 2023, 60(1): 30-42. DOI: 10.7544/issn1000-1239.202111244

    基于多级一致性协议的多核处理器WCET分析方法

    A WCET Analysis Method for Multi-Core Processors with Multi-Tier Coherence Protocol

    • 摘要: 由于多核处理器优越的计算性能,多核处理器现已广泛应用在嵌入式实时系统中. 相对于单核处理器,多核处理器存在资源共享竞争、并行任务干扰等因素,尤其是缓存(Cache)一致性问题,导致任务最坏情况执行时间(worst-case execution time,WCET)的预测更加困难.基于以上因素,提出基于多级一致性协议的多核处理器WCET分析方法.该方法针对多级一致性协议体系架构,提出多级一致性域的概念,将多核处理器的数据访问分为域内访问和跨域访问2个层次,根据Cache读写策略和MESI(modify exclusive shared invalid)一致性协议,得出一致性域内部和跨一致性域的Cache状态更新函数,从而实现多级一致性协议嵌套情况下的WCET分析.实验结果表明,在改变Cache配置参数的情况下,该方法分析结果与GEM5仿真结果的变化趋势一致,经过相关性分析,GEM5仿真结果与该方法分析结果相关性系数不低于0.98;在分析精度方面,该方法的平均过估计率为1.30,相比现有方法降低了0.78.

       

      Abstract: Due to the high parallel computing performance of multi-core processors, it has become a trend in real-time systems. Compared with single-core processors, the WCET (worst-case execution time) analysis of multi-core processors is confronted with greater challenges because of shared resources competition and parallel tasks interference. Especially, the Cache coherence protocol in multi-core processors makes WCET analysis more complex. We present a multi-tier coherence protocol WCET analysis method for multi-core processors with MESI coherence protocol based on the reasons above. Aiming at the architecture of multi-core processor with multi-tire coherence protocol, a multi-level consistency domain is defined which determines cores using the same coherence protocol. According to the access rules on memory hierarchy, the shared data access of multi-core processors is divided into intra-domain access and cross-domain access, proposing a Cache update function for multi-core processors with multi-tier coherence protocol. Thus, WCET analysis in the case of multi-tier coherence protocol nesting is realized. The experimental results show that the estimated results are consistent with the simulation results of GEM5 for different Cache configurations, and correlation analysis reveals that the estimated WCET is significantly correlated with simulation results. Furthermore, the average overestimation rate of this method is 1.30, which is decreased 0.78 than the representative related work.

       

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