Abstract: As semiconductor technology scales, chip physical design confronts escalating complexity and multi-objective optimization challenges, with traditional electronic design automation (EDA) tools encountering bottlenecks in computational efficiency and convergence. Artificial intelligence (AI), specifically deep learning (DL) and reinforcement learning (RL), offers a transformative paradigm for data-driven optimization in physical design. This survey systematically reviews the application of AI methods in the four core stages of chip physical design: floorplanning, placement, clock tree synthesis, and routing. First, from the perspective of optimization objectives, representative AI methods and their technical contributions in each stage are summarized. Second, a critical analysis of the gap between academic datasets and industrial scenarios is conducted, revealing key data bottlenecks. Third, the integration approaches between AI methods and traditional EDA flows across different stages are examined. Then, the evolutionary trends of AI methods in each stage are systematically reviewed, highlighting the paradigm shift from isolated, geometry-driven optimization toward cross-stage collaboration and AI-native chip physical design. Although AI methods have significantly improved design efficiency and quality, their widespread adoption is still limited by data scarcity, insufficient model interpretability, and challenges in integration with existing toolchains. Finally, we discuss the limitations of existing AI-driven approaches in physical chip design and outline promising research directions, including open-source AI-EDA infrastructure, large circuit foundation models, and AI-native EDA.