Abstract: Three dimensional integrated circuits (3D IC) and networks on chip (NoC) are two trends of integrated circuit design. Three dimensional networks on chip (3D NoC), which combines 3D IC and NoC, is one of the hot spots of current research. Existing 3D NoC researches paid inadequate attention to the feature of heterogeneous communication between inter and intra silicon wafer. This paper devises a kind of single hop inter dies (SHID) architecture which is a communication feature-aware architecture using heterogeneous topology and express inter dies router (EIDR). Analysis on the experimental data shows that compared with the existing 3D NoC structures of 3D-Mesh and NoC-Bus, SHID architecture has some characteristics: 1) The latency of SHID architecture is smaller. It is 15.1% less than 3D-Mesh and 11.5% less than NoC-Bus with stacking 4 layers; 2) The power consumption of SHID architecture equals NoC-Bus and it is 10% less than 3D-Mesh; 3) The throughput of SHID architecture decreases more slowly as the number of stacked layers increases. It is 66.98% larger than that of 3D-Mesh and 314.49% larger than that of NoC-Bus with stacking 16 layers. SHID architecture has more advantages in terms of both performance and scalability and is a well design choice for future 3D NoC architecture.