基于异步时钟的SoC功耗约束测试调度优化

凌立; 江建慧

doi:10.7544/issn1000-1239.2015.20148145

基于异步时钟的SoC功耗约束测试调度优化

凌立,
江建慧

(同济大学软件学院上海 201804) (jhjiang@tongji.edu.cn)

基金项目: 国家自然科学基金项目(61432017,61404092)；江苏省未来网络创新研究院未来网络前瞻性研究项目(BY2013095-5-06)

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中图分类号: TP391
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出版历程
- 发布日期: 2015-10-31

Power-Constrained SoC Test Scheduling Optimization Using Asynchronous Clock Periods

(School of Software Engineering, Tongji University, Shanghai 201804)

摘要

摘要: 测试调度是一种能有效减少片上系统(system-on-chip, SoC)测试耗时(test application time, TAT)以降低测试成本的经典技术.然而，随着功耗问题的日益加剧，功耗约束成为测试调度中必须考虑的重要问题.可以调节各测试周期长度的异步时钟测试在对单个电路进行测试用时优化时效果显著，但直接将其应用于SoC测试调度并非总能获得最优的调度结果，使用传统测试调度模型往往会产生明显非最优的结果.在结合图论中团(clique)的概念，并分析异步时钟机制的特点后，提出一种将异步时钟特性应用于功耗约束SoC测试调度的方案.使用测试兼容图(test compatibility graph, TCG)和混合整型线性规划(mixed integer linear programming, MILP)建立相对应数学模型，理论分析和在ITC02基准SoC集上的模拟实验结果表明，该方案能有效地减少测试耗时.
- SoC测试调度 /
- 功耗约束 /
- 异步时钟 /
- 混合整型线性规划模型 /
- 团
Abstract: Test cost of very large scale integration (VLSI) circuits is highly related to the test application time (TAT). Test scheduling is an effective technique to reduce the TAT of testing a SoC, which has been studied for decades. However, increasing power issues and consequences have made power-aware test necessary and important. Power-constrained test scheduling is one of the promising methods. Recently asynchronous clock test which can vary the clock period of each test cycle has been developed and shown great potential in TAT reduction for single circuit. However, applying such features to SoC test scheduling is not straight forward. Using conventional test scheduling model may lead to inferior results and longer scheduling time. After analyzing the characteristics of asynchronous clock test and power-constrained test scheduling problems, we propose a method to exploit asynchronous clock to SoC test scheduling based on clique. The resource constraint among each tests is represented by test-compatibility-graph (TCG); the scheduling problem is formed using mixed-integer linear programming (MILP) model; and the problem is solved by state-of-the-art mathematical programming solver. The results of both theoretical analysis and simulation experiment on the ITC02 benchmarks show that combining test scheduling technique with asynchronous clock can reduce TAT effectively and the proposed method can optimize the scheduling problem even further.
- SoC test scheduling /
- power constraint /
- asynchronous clock /
- mixed-integer linear programming (MILP) model /
- clique

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