Abstract: Test cost of very large scale integration (VLSI) circuits is highly related to the test application time (TAT). Test scheduling is an effective technique to reduce the TAT of testing a SoC, which has been studied for decades. However, increasing power issues and consequences have made power-aware test necessary and important. Power-constrained test scheduling is one of the promising methods. Recently asynchronous clock test which can vary the clock period of each test cycle has been developed and shown great potential in TAT reduction for single circuit. However, applying such features to SoC test scheduling is not straight forward. Using conventional test scheduling model may lead to inferior results and longer scheduling time. After analyzing the characteristics of asynchronous clock test and power-constrained test scheduling problems, we propose a method to exploit asynchronous clock to SoC test scheduling based on clique. The resource constraint among each tests is represented by test-compatibility-graph (TCG); the scheduling problem is formed using mixed-integer linear programming (MILP) model; and the problem is solved by state-of-the-art mathematical programming solver. The results of both theoretical analysis and simulation experiment on the ITC02 benchmarks show that combining test scheduling technique with asynchronous clock can reduce TAT effectively and the proposed method can optimize the scheduling problem even further.