Abstract: In recent years, as Moore’s Law approaches the limit, the development of system on chip (SoC) has encountered bottlenecks. Integrating more functional units and larger on-chip storage makes the chip area increase sharply, resulting in a decrease in chip’s yield, which in turn increases costs. In order to break through the limitations of Moore’s Law, research institutions and chip manufacturers began to seek to use advanced connection and packaging technology to disassemble the original chip into multiple smaller, higher-yielding, and cost-effective Chiplets and then reassemble them. This packaging technology is similar to the system in package (SiP) of the chip. At present, there is no unified standard for the packaging methods of Chiplets, the feasible solutions include chip splicing through silicon bridges or chip connection through interposers, etc., which can be divided into 2D, 2.5D, 3D according to the packaging structure. By summarizing the currently released Chiplets products, we discuss the advantages and disadvantages of each structure. In addition, the communication structure between multiple Chiplets is also the focus of research. How to implement a traditional bus or network on chip (NoC) on Chiplets? This paper explores the development trend and direction of Chiplets in the future through discussion of existing technologies.