Abstract: The high-performance global routing results can effectively meet the design specifications and greatly improve the efficiency of the detailed routing phase. As the signal transmitted in the chip increases through the bus, the bus gradually becomes a key factor affecting the performance of the chip. If the bus topology structure is not considered during the global routing stage, coupling phenomena will occur when the bus transmission information is transmitted, resulting in a large timing deviation of signal transmission. Therefore, in order to optimize the consistency of bus topology structure in 2D global routing, an effective multi-strategy bus topology aware global routing algorithm is proposed. First, a topology reconstruction strategy based on congestion is designed to optimize the two-pin net and improve the utilization rate of routing space effectively. Second, a heuristic reroute model is constructed to realize the reroute of multi-signal bit bus. Third, a routing algorithm consider topology structure is added to the rip-up and reroute model to adjust the topology structure of the same bus net group and improve the consistency of bus topology. Finally, an iterative method to adjust the cost of bus topology is designed to further optimize the consistency of bus topology. Experimental results show that the proposed algorithm can effectively optimize the bus topology consistency of 2D routing solution.