Abstract: The Chiplet-integrated chip based on advanced packaging technology offers a number of advantages in terms of manufacturing cost, design efficiency and special customization, etc. This represents a new and effective method of maintaining the performance growth of the chip in the post-Moore era. As an important method of quantitative analysis of architectural design, design space exploration (DSE) can assist designers in comprehending and evaluating the intricate interrelationships between design parameters. However, when applying the traditional DSE method directly to the Chiplet design, it gives rise to issues such as incomplete evaluation, inaccurate simulation, and low efficiency. The solution to these problems is FireLink, an evaluation framework for Chiplet design space exploration. FireLink supports the modelling and simulation of Chiplet microarchitectures and interconnection networks, and is capable of efficiently evaluating performance, power, area and cost metrics. Furthermore, experiments were conducted using the Iterative Dichotomiser 3 (ID3) machine learning algorithm in this framework, which has been demonstrated to effectively improve the efficiency of DSE. In comparison to existing DSE methodologies, FireLink exhibits notable advantages in comprehensiveness of evaluating, completeness of modeling and efficiency of DSE, therefore designers can explore a wider range of design space in a shorter time, so as to select a better Chiplet design scheme.