Abstract: As the breaker of Moore’s Law, Chiplet technology has high expectations in the integrated circuit industry. Chiplet technology can combine multiple small chips with specific functions into a Chiplet integrated chip through high-speed interconnection technology, whose core technology is the Chiplet interconnection technology that can achieve Chiplet combination and expansion. We analyze and discuss the Chiplet interconnection protocol, interconnection architecture, fault-tolerant mechanism, typical interconnection Chiplets, and testability design based on the interconnection Chiplet. Firstly, we provide a detailed comparison and analysis of domestic and foreign Chiplet interconnection protocols, and provide the layers and functions of each protocol. Secondly, we introduce three typical Chiplet interconnection architectures, and analyze the characteristics and advantages of each architecture. Afterwards, the Chiplet fault-tolerant mechanism is introduced, including fault-tolerant encoding of interconnection interfaces, fault-tolerant topology, and fault-tolerant routing. Then, three types of interconnection Chiplet design schemes are presented, including programmable interconnection Chiplets, path programmable interconnection Chiplets, and fully customized interconnection Chiplets. Finally, a testability design testing scheme based on the interconnection Chiplet is introduced. This paper focuses on Chiplet interconnection and aims to help readers have a systematic understanding of Chiplet interconnection technology.